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cleaning verilog file lines

This commit is contained in:
tangxifan 2019-11-03 17:58:18 -07:00
parent 0ec465d4e1
commit 1fb29df1e2
1 changed files with 10 additions and 10 deletions
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20
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
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@ -399,16 +399,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
/* TODO: this is an old function, to be shadowed */ /* TODO: this is an old function, to be shadowed */
dump_verilog_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, top_testbench_file_path.c_str(), dump_verilog_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, top_testbench_file_path.c_str(),
src_dir_path, *(Arch.spice)); src_dir_path, *(Arch.spice));
/* TODO: new function: to be tested */
print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream,
sram_verilog_orgz_info->type,
Arch.spice->circuit_lib, global_ports,
L_logical_blocks, device_size, L_grids, L_blocks,
std::string(chomped_circuit_name),
std::string(top_testbench_file_path + std::string(".bak")),
std::string(src_dir_path),
std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file),
Arch.spice->spice_params);
} }
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) { if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) {
@ -461,6 +451,16 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name,
autocheck_top_testbench_file_path.c_str(), src_dir_path, autocheck_top_testbench_file_path.c_str(), src_dir_path,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
/* TODO: new function: to be tested */
print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream,
sram_verilog_orgz_info->type,
Arch.spice->circuit_lib, global_ports,
L_logical_blocks, device_size, L_grids, L_blocks,
std::string(chomped_circuit_name),
std::string(autocheck_top_testbench_file_path + std::string(".bak")),
std::string(src_dir_path),
std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file),
Arch.spice->spice_params);
} }
/* Output Modelsim Autodeck scripts */ /* Output Modelsim Autodeck scripts */