diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h
index 53893fe62..19109ce21 100644
--- a/openfpga/src/base/openfpga_verilog_template.h
+++ b/openfpga/src/base/openfpga_verilog_template.h
@@ -62,11 +62,9 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
   if (g_vpr_ctx.device().arch->perimeter_cb) {
     options.set_constant_undriven_inputs(true);
     VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n");
-    if (!cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) {
-      VTR_LOG("User forces to disable the constant_undriven_input option even when perimeter connection blocks are enabled\n");
-    }
+  } else {
+    options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs));
   }
-  options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs));
 
   return fpga_fabric_verilog(
     openfpga_ctx.mutable_module_graph(),
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 1c5ce17ad..3b52c2d87 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -619,8 +619,7 @@ void write_verilog_module_to_file(
     for (std::pair<std::string, std::vector<BasicPort>> port_group :
          local_undriven_wires) {
       for (const BasicPort& local_undriven_wire : port_group.second) {
-        fp << generate_verilog_port_constant_values(local_undriven_wire, std::vector<size_t>(local_undriven_wire.get_width(), 0), false) << ";"
-           << std::endl;
+        print_verilog_wire_constant_values(fp, local_undriven_wire, std::vector<size_t>(local_undriven_wire.get_width(), 0));
       }
     }
   }