From 1ef38b6a6498edc27f9bebd307dfd159ce1d29c3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 20 Sep 2023 20:34:21 -0700 Subject: [PATCH] [core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming --- openfpga/src/fabric/build_tile_modules.cpp | 14 ++++---------- .../build_top_module_child_tile_instance.cpp | 12 ++++-------- 2 files changed, 8 insertions(+), 18 deletions(-) diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index ea39471f9..b11ee2a45 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -203,9 +203,7 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( std::string temp_sb_module_name = generate_switch_block_module_name( fabric_tile.sb_coordinates(fabric_tile_id)[isb]); if (name_module_using_index) { - temp_sb_module_name = generate_switch_block_module_name_using_index( - device_rr_gsb.get_sb_unique_module_index( - fabric_tile.sb_coordinates(fabric_tile_id)[isb])); + temp_sb_module_name = generate_switch_block_module_name_using_index(isb); } src_grid_port.set_name(generate_tile_module_port_name( temp_sb_module_name, sink_sb_port.get_name())); @@ -437,8 +435,7 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( if (name_module_using_index) { cb_instance_name_in_tile = generate_connection_block_module_name_using_index( - cb_type, device_rr_gsb.get_cb_unique_module_index( - cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type))); + cb_type, icb); } src_cb_port.set_name(generate_tile_module_port_name( cb_instance_name_in_tile, src_cb_port.get_name())); @@ -703,9 +700,7 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( std::string temp_sb_module_name = generate_switch_block_module_name( fabric_tile.sb_coordinates(fabric_tile_id)[isb]); if (name_module_using_index) { - temp_sb_module_name = generate_switch_block_module_name_using_index( - device_rr_gsb.get_sb_unique_module_index( - fabric_tile.sb_coordinates(fabric_tile_id)[isb])); + temp_sb_module_name = generate_switch_block_module_name_using_index(isb); } chan_input_port.set_name(generate_tile_module_port_name( temp_sb_module_name, chan_input_port.get_name())); @@ -926,8 +921,7 @@ static int build_tile_module_ports_from_cb( if (name_module_using_index) { cb_instance_name_in_tile = generate_connection_block_module_name_using_index( - cb_type, device_rr_gsb.get_cb_unique_module_index( - cb_type, unique_rr_gsb.get_cb_coordinate(cb_type))); + cb_type, icb); } vtr::Point tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index c56171ea6..416bbbeb3 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -306,8 +306,7 @@ static int build_top_module_tile_nets_between_sb_and_pb( generate_switch_block_module_name(sink_sb_coord_in_unique_tile); if (name_module_using_index) { sink_sb_instance_name_in_unique_tile = - generate_switch_block_module_name_using_index( - device_rr_gsb.get_sb_unique_module_index(sink_sb_coord_in_unique_tile)); + generate_switch_block_module_name_using_index(sb_idx_in_curr_fabric_tile); } /* We could have two different coordinators, one is the instance, the other is @@ -547,8 +546,7 @@ static int build_top_module_tile_nets_between_cb_and_pb( if (name_module_using_index) { src_cb_instance_name_in_unique_tile = generate_connection_block_module_name_using_index( - cb_type, device_rr_gsb.get_cb_unique_module_index( - cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type))); + cb_type, cb_idx_in_curr_fabric_tile); } /* We could have two different coordinators, one is the instance, the other is @@ -750,8 +748,7 @@ static int build_top_module_tile_nets_between_sb_and_cb( generate_switch_block_module_name(sb_coord_in_unique_tile); if (name_module_using_index) { sb_instance_name_in_unique_tile = - generate_switch_block_module_name_using_index( - device_rr_gsb.get_sb_unique_module_index(sb_coord_in_unique_tile)); + generate_switch_block_module_name_using_index(sb_idx_in_curr_fabric_tile); } /* Skip those Switch blocks that do not exist */ @@ -857,8 +854,7 @@ static int build_top_module_tile_nets_between_sb_and_cb( if (name_module_using_index) { cb_instance_name_in_unique_tile = generate_connection_block_module_name_using_index( - cb_type, device_rr_gsb.get_cb_unique_module_index( - cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type))); + cb_type, cb_idx_in_cb_tile); } std::string cb_tile_module_name = generate_tile_module_name(cb_unique_tile_coord);