Merge remote-tracking branch 'upstream/master' into update_from_upstream

.dockerignore

@@ -12,12 +12,12 @@
 !/openfpga/openfpga
 !/vpr/libvpr.a
 !/vpr/vpr
-!/yosys/share/
+!/yosys/install/share/
-!/yosys/yosys
+!/yosys/install/bin/yosys
-!/yosys/yosys-abc
+!/yosys/install/bin/yosys-abc
-!/yosys/yosys-config
+!/yosys/install/bin/yosys-config
-!/yosys/yosys-filterlib
+!/yosys/install/bin/yosys-filterlib
-!/yosys/yosys-smtbmc
+!/yosys/install/bin/yosys-smtbmc
 !/openfpga_flow
 !/openfpga.sh
 !/openfpga_flow/

.github/workflows/build.yml

@@ -170,12 +170,12 @@ jobs:
             openfpga/openfpga
             vpr/libvpr.a
             vpr/vpr
-            yosys/share/
+            yosys/install/share/
-            yosys/yosys
+            yosys/install/bin/yosys
-            yosys/yosys-abc
+            yosys/install/bin/yosys-abc
-            yosys/yosys-config
+            yosys/install/bin/yosys-config
-            yosys/yosys-filterlib
+            yosys/install/bin/yosys-filterlib
-            yosys/yosys-smtbmc
+            yosys/install/bin/yosys-smtbmc
             openfpga_flow
             openfpga.sh
   docker_distribution:
@@ -240,11 +240,11 @@ jobs:
           chmod +x ace2/ace
           chmod +x openfpga/openfpga
           chmod +x vpr/vpr
-          chmod +x yosys/yosys
+          chmod +x yosys/install/bin/yosys
-          chmod +x yosys/yosys-abc
+          chmod +x yosys/install/bin/yosys-abc
-          chmod +x yosys/yosys-config
+          chmod +x yosys/install/bin/yosys-config
-          chmod +x yosys/yosys-filterlib
+          chmod +x yosys/install/bin/yosys-filterlib
-          chmod +x yosys/yosys-smtbmc
+          chmod +x yosys/install/bin/yosys-smtbmc
       - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
         shell: bash
         run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh

.gitmodules

@@ -1,4 +1,8 @@
 [submodule "yosys"]
 	path = yosys
 	url = https://github.com/YosysHQ/yosys
-    branch = release-branch-0.10
+	branch = release-branch-0.10
+	ignore = dirty
+[submodule "yosys-plugins"]
+	path = yosys-plugins
+	url = https://github.com/SymbiFlow/yosys-symbiflow-plugins

CMakeLists.txt

@@ -231,13 +231,24 @@ include(CheckCXXCompilerFlag)
 add_custom_target(
     yosys ALL 
     COMMAND $(MAKE) config-gcc
-    COMMAND $(MAKE) 
+    COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys
     COMMENT "Compile Yosys with given Makefile"
 )
 
 # yosys compilation ends
 
+# yosys-plugins compilation starts
+add_custom_target(
+    yosys-plugins ALL
+    COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql"
+    WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins
+    DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys
+    COMMENT "Compile Yosys-plugins with given Makefile"
+)
+
+add_dependencies(yosys-plugins yosys)
+
 # run make to extract compiler options, linker options and list of source files
 #add_custom_target(
 #  yosys

Makefile

@@ -21,7 +21,7 @@ compile:
 	cd build && $(MAKE)
 
 clean:
-	rm -rf build
+	rm -rf build yosys/install
 
 build/Makefile:
 	make checkout

docker/Dockerfile.master

@@ -3,7 +3,7 @@ RUN mkdir -p /opt/openfpga
 WORKDIR /opt/openfpga
 COPY . /opt/openfpga
 RUN chmod +x abc/abc ace2/ace openfpga/openfpga vpr/vpr
-RUN chmod +x yosys/yosys yosys/yosys-abc yosys/yosys-config yosys/yosys-filterlib yosys/yosys-smtbmc
+RUN chmod +x yosys/install/bin/yosys yosys/install/bin/yosys-abc yosys/install/bin/yosys-config yosys/install/bin/yosys-filterlib yosys/install/bin/yosys-smtbmc
-ENV PATH="/opt/openfpga/openfpga:/opt/openfpga/yosys:${PATH}"
+ENV PATH="/opt/openfpga/openfpga:/opt/openfpga/yosys/install/bin:${PATH}"
 ENV PATH="/opt/openfpga/ace2:/opt/openfpga/abc:/opt/openfpga/vpr:${PATH}"
 ENV OPENFPGA_PATH="/opt/openfpga"

docs/source/manual/openfpga_flow/run_fpga_flow.rst

@@ -109,8 +109,20 @@ General Arguments
 
 .. option:: --yosys_tmpl <yosys_template_file>
 
-    This option allows the user to provide a custom Yosys template
+    This option allows the user to provide a custom Yosys template while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Alternately, user can create a copy and modify according to their need. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables. In case if ``--verific`` option is provided then ``ADD_INCLUDE_DIR``, ``ADD_LIBRARY_DIR``, ``ADD_BLACKBOX_MODULES``, ``READ_HDL_FILE`` (should be used instead of ``READ_VERILOG_FILE``) and ``READ_LIBRARY`` additional varialbes are supported. The variables can be used as ``${var_name}``.
-    While running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables, which can be used as ``${var_name}``. Alternately, user can create a copy and modify according to their need.
+
+.. option:: --ys_rewrite_tmpl <yosys_rewrite_template_file>
+
+    This option allows the user to provide an alternate Yosys template to rewrite Verilog netlist while running a yosys_vpr flow. The alternate Yosys template script supports all of the main Yosys template script variables.
+
+.. option:: --verific
+
+    This option specifies to use Verific as a frontend for Yosys while running a yosys_vpr flow.
+    The following standards are used by default for reading input HDL files:
+    * Verilog - ``vlog95``
+    * System Verilog - ``sv2012``
+    * VHDL - ``vhdl2008``
+    The option should be used only with custom Yosys template containing Verific commands.
 
 .. option:: --debug
 

docs/source/manual/openfpga_flow/run_fpga_task.rst

@@ -94,7 +94,7 @@ Declaring all the above sections are mandatory.
 General Section
 ^^^^^^^^^^^^^^^
 
-.. option:: fpga_flow==<yosys_vpr|vpr_blif>
+.. option:: fpga_flow=<yosys_vpr|vpr_blif>
 
     This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
 
@@ -118,7 +118,72 @@ General Section
 
 .. option:: timeout_each_job=<true|false>
 
-    Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min. ``
+    Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min.``
+
+.. option:: verific=<true|false>
+
+    Specifies to use Verific as a frontend for Yosys while running a yosys_vpr flow.
+    The following standards are used by default for reading input HDL files:
+    * Verilog - ``vlog95``
+    * System Verilog - ``sv2012``
+    * VHDL - ``vhdl2008``
+    The option should be used only with custom Yosys template containing Verific commands.
+
+
+OpenFPGA_SHELL Sections
+^^^^^^^^^^^^^^^^^^^^^^^
+
+    User can specify OpenFPGA_SHELL options in this section.
+
+.. option:: verific_include_dir=<include_dir>
+
+   The ``include_dir`` is path to the Verilog/VHDL include directory. If there are multiple paths then they can be
+   provided as a comma separated list.
+
+.. option:: verific_library_dir=<library_dir>
+
+   The ``library_dir`` is path to the Verilog/VHDL library directory. Verific will search in this directory to
+   find undefined modules. If there are multiple paths then they can be provided as a comma separated list.
+
+.. option:: verific_verilog_standard=<-vlog95|-vlog2k>
+
+   The option specifies Verilog language standard to be used while reading the Verilog files.
+
+.. option:: verific_systemverilog_standard=<-sv2005|-sv2009|-sv2012>
+
+   The option specifies SystemVerilog language standard to be used while reading the SystemVerilog files.
+
+.. option:: verific_vhdl_standard=<-vhdl87|-vhdl93|-vhdl2k|-vhdl2008>
+
+   The option specifies VHDL language standard to be used while reading the VHDL files.
+
+.. option:: verific_read_lib_name=<lib_name>
+
+   The option specifies library name where Verilog/SystemVerilog/VHDL files specified by ``verific_read_lib_src`` option will be loaded. This option should be used only with ``verific_read_lib_src`` option.
+
+.. option:: verific_read_lib_src=<library_src_files>
+
+   The option specifies Verilog/SystemVerilog/VHDL files to be loaded into library specified by ``verific_read_lib_name`` option. The ``library_src_files`` should be the source files names separated by commas. This option should be used only with ``verific_read_lib_name`` option.
+
+.. option:: verific_search_lib=<lib_name>
+
+   The option specifies library name from where will look up for external definitions while reading HDL files.
+
+.. option:: yosys_cell_sim_verilog=<verilog_files>
+
+   The option specifies Verilog files which should be separated by comma.
+
+.. option:: yosys_cell_sim_systemverilog=<systemverilog_files>
+
+   The option specifies SystemVerilog files which should be separated by comma.
+
+.. option:: yosys_cell_sim_vhdl=<vhdl_files>
+
+   The option specifies VHDL files which should be separated by comma.
+
+.. option:: yosys_blackbox_modules=<blackbox_modules>
+
+   The option specifies blackbox modules names which should be separated by comma (usually these are the modules defined in files specified with yosys_cell_sim_<verilog/systemverilog/vhdl> option).
 
 
 Architectures Sections

openfpga_flow/benchmarks/micro_benchmark/and2/and2_verific.blif

@@ -0,0 +1,7 @@
+# Benchmark "and2" written by ABC on Wed Oct 27 18:22:37 2021
+.model and2
+.inputs a b 
+.outputs c 
+.names a b c
+11 1
+.end

openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch_verific.blif

@@ -0,0 +1,12 @@
+# Benchmark "and2_latch" written by ABC on Wed Oct 27 18:22:39 2021
+.model and2_latch
+.inputs a b clk 
+.outputs c d 
+
+.latch n11 d re clk 2
+
+.names a b c
+11 1
+.names c n11
+1 1
+.end

openfpga_flow/benchmarks/micro_benchmark/or2/or2_verific.blif

@@ -0,0 +1,7 @@
+# Benchmark "or2" written by ABC on Wed Oct 27 18:22:37 2021
+.model or2
+.inputs a b 
+.outputs c 
+.names a b c
+00 0
+.end

openfpga_flow/misc/fpgaflow_default_tool_path.conf

@@ -1,10 +1,10 @@
 # Standard Configuration Example
 [CAD_TOOLS_PATH]
 openfpga_shell_path = ${PATH:OPENFPGA_PATH}/openfpga/openfpga
-yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys
+yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
 misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
 odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
-abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc
+abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
 abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
 abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
 vpr_path = ${PATH:OPENFPGA_PATH}/vpr/vpr

openfpga_flow/misc/qlf_yosys.ys

@@ -1,7 +1,10 @@
 # Yosys synthesis script for ${TOP_MODULE}
+
+plugin -i ql-qlf
+
 # Read verilog files
 ${READ_VERILOG_FILE}
 
-synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
+synth_ql -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
 
 write_verilog -noattr -nohex ${OUTPUT_VERILOG}

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -137,6 +137,9 @@ run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_l
 run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
 run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
 
+echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific";
+run-task basic_tests/verific_test --debug --show_thread_logs
+
 # Repgression test to test multi-user enviroment
 cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
 cd /tmp/ && run-task configuration_chain --debug --show_thread_logs

openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh

@@ -10,9 +10,9 @@ echo -e "QuickLogic regression tests";
 
 # TODO: Disabled all the tests here because Quicklogic's synthesis script is not in Yosys v0.10 release. Will bring back once Quicklogic manages to merge their contribution to Yosys upstream
 
-##echo -e "Testing yosys flow using custom ys script for running quicklogic device";
+echo -e "Testing yosys flow using custom ys script for running quicklogic device";
-##run-task quicklogic_tests/flow_test --debug --show_thread_logs
+run-task quicklogic_tests/flow_test --debug --show_thread_logs
-##
+
 ##echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
 ##run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
 ##run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs

openfpga_flow/scripts/run_fpga_flow.py

@@ -101,6 +101,8 @@ parser.add_argument('--yosys_tmpl', type=str, default=None,
                     help="Alternate yosys template, generates top_module.blif")
 parser.add_argument('--ys_rewrite_tmpl', type=str, default=None,
                     help="Alternate yosys template, to rewrite verilog netlist")
+parser.add_argument('--verific', action="store_true",
+                    help="Run yosys with verific enabled")
 parser.add_argument('--disp', action="store_true",
                     help="Open display while running VPR")
 parser.add_argument('--debug', action="store_true",
@@ -465,11 +467,7 @@ def clean_up_and_exit(msg, clean=False):
     logger.error("Exiting . . . . . .")
     exit(1)
 
-
+def create_yosys_params():
-def run_yosys_with_abc():
-    """
-    Execute yosys with ABC and optional blackbox support
-    """
     tree = ET.parse(args.arch_file)
     root = tree.getroot()
     try:
@@ -484,18 +482,105 @@ def run_yosys_with_abc():
     args.K = lut_size
     # Yosys script parameter mapping
     ys_params = script_env_vars["PATH"]
-    ys_params["READ_VERILOG_FILE"] = " \n".join([
-            "read_verilog -nolatches " + shlex.quote(eachfile)
-            for eachfile in args.benchmark_files])
-    ys_params["TOP_MODULE"] = args.top_module
-    ys_params["LUT_SIZE"] = lut_size
-    ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif"
-    ys_params["OUTPUT_VERILOG"] = args.top_module+"_output_verilog.v"
 
     for indx in range(0, len(OpenFPGAArgs), 2):
         tmpVar = OpenFPGAArgs[indx][2:].upper()
         ys_params[tmpVar] = OpenFPGAArgs[indx+1]
 
+    if not args.verific:
+        ys_params["READ_VERILOG_FILE"] = " \n".join([
+            "read_verilog -nolatches " + shlex.quote(eachfile)
+            for eachfile in args.benchmark_files])
+    else:
+        if "ADD_INCLUDE_DIR" not in ys_params:
+            ys_params["ADD_INCLUDE_DIR"] = ""
+        if "ADD_LIBRARY_DIR" not in ys_params:
+            ys_params["ADD_LIBRARY_DIR"] = ""
+        if "ADD_BLACKBOX_MODULES" not in ys_params:
+            ys_params["ADD_BLACKBOX_MODULES"] = ""
+        if "READ_HDL_FILE" not in ys_params:
+            ys_params["READ_HDL_FILE"] = ""
+        if "READ_LIBRARY" not in ys_params:
+            ys_params["READ_LIBRARY"] = ""
+        if "VERIFIC_VERILOG_STANDARD" not in ys_params:
+            ys_params["VERIFIC_VERILOG_STANDARD"] = "-vlog2k"
+        if "VERIFIC_SYSTEMVERILOG_STANDARD" not in ys_params:
+            ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"] = "-sv"
+        if "VERIFIC_VHDL_STANDARD" not in ys_params:
+            ys_params["VERIFIC_VHDL_STANDARD"] = "-vhdl"
+        ext_to_standard_map = {
+            ".v" : ys_params["VERIFIC_VERILOG_STANDARD"],
+            ".vh" : ys_params["VERIFIC_VERILOG_STANDARD"],
+            ".verilog" : ys_params["VERIFIC_VERILOG_STANDARD"],
+            ".vlg" : ys_params["VERIFIC_VERILOG_STANDARD"],
+            ".sv" : ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
+            ".svh" : ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
+            ".vhd" : ys_params["VERIFIC_VHDL_STANDARD"],
+            ".vhdl" : ys_params["VERIFIC_VHDL_STANDARD"]
+            }
+        lib_files = []
+        include_dirs = set([os.path.dirname(eachfile) for eachfile in args.benchmark_files])
+        if "VERIFIC_INCLUDE_DIR" in ys_params:
+            include_dirs.update(ys_params["VERIFIC_INCLUDE_DIR"].split(","))
+        if include_dirs and not ys_params["ADD_INCLUDE_DIR"]:
+            ys_params["ADD_INCLUDE_DIR"] = "\n".join(["verific -vlog-incdir " +
+                shlex.quote(eachdir) for eachdir in include_dirs])
+        if "VERIFIC_LIBRARY_DIR" in ys_params:
+            ys_params["ADD_LIBRARY_DIR"] = "\n".join(["verific -vlog-libdir " +
+                shlex.quote(eachdir) for eachdir in ys_params["VERIFIC_LIBRARY_DIR"].split(",")])
+        try:
+            if "VERIFIC_READ_LIB_NAME" in ys_params and "VERIFIC_READ_LIB_SRC" in ys_params:
+                for name in ys_params["VERIFIC_READ_LIB_SRC"].split(","):
+                    for eachfile in args.benchmark_files:
+                        if name in eachfile:
+                            lib_files.append(eachfile)
+                            break
+                if not lib_files:
+                    clean_up_and_exit("Failed to locate verific library files")
+                filename, file_extension = os.path.splitext(lib_files[0])
+                ys_params["READ_LIBRARY"] = " ".join(["verific -work",
+                    ys_params["VERIFIC_READ_LIB_NAME"], ext_to_standard_map[file_extension]] +
+                    [shlex.quote(eachfile) for eachfile in lib_files])
+            for eachfile in args.benchmark_files:
+                if eachfile in lib_files:
+                    continue
+                filename, file_extension = os.path.splitext(eachfile)
+                ys_params["READ_HDL_FILE"] += " ".join(["verific",
+                    "-L " + ys_params["VERIFIC_SEARCH_LIB"] if "VERIFIC_SEARCH_LIB" in ys_params else "",
+                    ext_to_standard_map[file_extension],
+                    shlex.quote(eachfile), "\n"])
+        except:
+            logger.exception("Failed to determine design file type")
+            clean_up_and_exit("")
+        if "YOSYS_CELL_SIM_VERILOG" in ys_params:
+            ys_params["READ_HDL_FILE"] += " ".join(["verific",
+                ys_params["VERIFIC_VERILOG_STANDARD"],
+                ys_params["YOSYS_CELL_SIM_VERILOG"], "\n"])
+        if "YOSYS_CELL_SIM_SYSTEMVERILOG" in ys_params:
+            ys_params["READ_HDL_FILE"] += " ".join(["verific",
+                ys_params["VERIFIC_SYSTEMVERILOG_STANDARD"],
+                ys_params["YOSYS_CELL_SIM_SYSTEMVERILOG"], "\n"])
+        if "YOSYS_CELL_SIM_VHDL" in ys_params:
+            ys_params["READ_HDL_FILE"] += " ".join(["verific",
+                ys_params["VERIFIC_VHDL_STANDARD"],
+                ys_params["YOSYS_CELL_SIM_VHDL"], "\n"])
+        if "YOSYS_BLACKBOX_MODULES" in ys_params:
+            ys_params["ADD_BLACKBOX_MODULES"] = ("blackbox " +
+            " ".join(["\\" + mod for mod in ys_params["YOSYS_BLACKBOX_MODULES"].split(",")]))
+
+    ys_params["TOP_MODULE"] = args.top_module
+    ys_params["LUT_SIZE"] = lut_size
+    ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif"
+    ys_params["OUTPUT_VERILOG"] = args.top_module+"_output_verilog.v"
+
+    return ys_params
+
+
+def run_yosys_with_abc():
+    """
+    Execute yosys with ABC and optional blackbox support
+    """
+    ys_params = create_yosys_params()
     yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
         cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
     tmpl = Template(open(yosys_template, encoding='utf-8').read())
@@ -705,19 +790,7 @@ def run_rewrite_verilog():
         run_command("Yosys", "yosys_rewrite.log", command)
     else:
         # Yosys script parameter mapping
-        ys_rewrite_params = {
+        ys_rewrite_params = create_yosys_params()
-            "READ_VERILOG_FILE": " \n".join([
-                "read_verilog -nolatches " + shlex.quote(eachfile)
-                for eachfile in args.benchmark_files]),
-            "TOP_MODULE": args.top_module,
-            "OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
-            "INPUT_BLIF": args.top_module+".blif",
-            "OUTPUT_VERILOG": args.top_module+"_output_verilog.v"
-        }
-
-        for indx in range(0, len(OpenFPGAArgs), 2):
-            tmpVar = OpenFPGAArgs[indx][2:].upper()
-            ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx + 1]
 
         # Split a series of scripts by delim ';'
         # And execute the scripts serially
@@ -726,7 +799,7 @@ def run_rewrite_verilog():
             logger.info("Yosys rewrite iteration: " + str(iteration_idx))
             with open("yosys_rewrite_" + str(iteration_idx) + ".ys", 'w') as archfile:
                 archfile.write(tmpl.safe_substitute(ys_rewrite_params))
-            run_command("Run yosys", "yosys_rewrite_output.log",
+            run_command("Run yosys", "yosys_rewrite_output_" + str(iteration_idx) + ".log",
                     [cad_tools["yosys_path"], "yosys_rewrite_" + str(iteration_idx) + ".ys"])
 
 

openfpga_flow/scripts/run_fpga_task.py

@@ -398,6 +398,9 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
     if task_gc.get("fpga_flow"):
         command += ["--fpga_flow", task_gc.get("fpga_flow")]
 
+    if task_gc.getboolean("verific"):
+        command += ["--verific"]
+
     if task_gc.get("run_engine") == "openfpga_shell":
         for eachKey in task_OFPGAc.keys():
             command += [f"--{eachKey}",

openfpga_flow/tasks/basic_tests/verific_test/config/task.conf

@@ -0,0 +1,50 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=
+openfpga_fast_configuration=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2_verific.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2_verific.blif
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch_verific.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+bench1_top = or2
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
+bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+bench2_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=

openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf

@@ -26,58 +26,58 @@ yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rtl/*.v
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rtl/*.v
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v
 bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/counter.v
-bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
+#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
-bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
+#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
-bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
+#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
 #cavlc_top requires async reset/preset
 #bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v
-bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
+#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
 # counter120bitx5 requires 5 clocks
 #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v
-bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_16bit/rtl/*.v
+#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_16bit/rtl/*.v
-bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v
+#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v
-bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v
+#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v
-bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v
+#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v
 #i2c_master_top requires async reset/preset
 #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v
 #iir requires async reset/preset
 #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v
 #jpeg_qnr requires async reset/preset
 #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
-bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
+#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
 # sdc_controller requires 4 clocks
 #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
 
 [SYNTHESIS_PARAM]
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
 
-bench0_top = io_tc1
+#bench0_top = io_tc1
-bench1_top = unsigned_mult_80
+#bench1_top = unsigned_mult_80
-bench2_top = bin2bcd
+#bench2_top = bin2bcd
 bench3_top = counter
-bench5_top = rs_decoder_top
+#bench5_top = rs_decoder_top
-bench6_top = top_module
+#bench6_top = top_module
-bench7_top = sha256 
+#bench7_top = sha256 
-bench8_top = cavlc_top
+#bench8_top = cavlc_top
 #bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench9_top = cf_fft_256_8
+#bench9_top = cf_fft_256_8
 #bench10_top = counter120bitx5
 #bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
-bench11_top = top
+#bench11_top = top
-bench12_top = dct_mac 
+#bench12_top = dct_mac 
-bench13_top = des_perf
+#bench13_top = des_perf
-bench14_top = diffeq_f_systemC 
+#bench14_top = diffeq_f_systemC 
-bench15_top = i2c_master_top 
+#bench15_top = i2c_master_top 
 #bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench16_top = iir
+#bench16_top = iir
 #bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench17_top = jpeg_qnr
+#bench17_top = jpeg_qnr
 #bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench18_top = multi_enc_decx2x4 
+#bench18_top = multi_enc_decx2x4 
 # sdc_controller requires 4 clocks
 #bench19_top = sdc_controller
 #bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys

yosys-plugins

@@ -0,0 +1 @@
+Subproject commit c44f188756783b2a9bc7197a0c72fd3f3698da1f