Merge pull request #529 from lnis-uofu/counters

Enable comprehensive tests for counter benchmarks
2022-02-14 18:27:20 -08:00 · 2022-02-14 18:27:20 -08:00 · 1e8deae120
parent a80b2d7882 be8f18310d
commit 1e8deae120
16 changed files with 264 additions and 14 deletions
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@ -53,6 +53,7 @@ constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
 *******************************************************************/
 static 
 void print_verilog_top_random_testbench_ports(std::fstream& fp,
+                                              const ModuleManager& module_manager,
                                              const std::string& circuit_name,
                                              const std::vector<std::string>& clock_port_names,
                                              const AtomContext& atom_ctx,
@ -79,7 +80,8 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
  /* Add an empty line as splitter */
  fp << std::endl;

-  print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
+  print_verilog_testbench_shared_ports(fp, module_manager, FabricGlobalPortInfo(), PinConstraints(),
+                                       atom_ctx, netlist_annotation,
                                       clock_port_names,
                                       std::string(),
                                       std::string(BENCHMARK_PORT_POSTFIX),
@ -308,7 +310,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
  std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);

  /* Start of testbench */
-  print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options);
+  print_verilog_top_random_testbench_ports(fp, module_manager, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options);

  /* Call defined top-level module */
  print_verilog_random_testbench_fpga_instance(fp, circuit_name,
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@ -185,13 +185,15 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,

    /* For other ports, give an default value */
    for (size_t pin_id = 0; pin_id < module_global_port.pins().size(); ++pin_id) {
-      BasicPort module_global_pin(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
+      BasicPort module_global_pin(module_global_port.get_name(),
                                  module_global_port.pins()[pin_id],
                                  module_global_port.pins()[pin_id]);

      /* If the global port name is in the pin constraints, we should wire it to the constrained pin */
      std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);

+      module_global_pin.set_name(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
+
      /* - If constrained to a given net in the benchmark, we connect the global pin to the net
       * - If constrained to an open net in the benchmark, we assign it to a default value 
       */
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@ -719,6 +719,9 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
 *    same input vectors
 *******************************************************************/
 void print_verilog_testbench_shared_ports(std::fstream& fp,
+                                          const ModuleManager& module_manager,
+                                          const FabricGlobalPortInfo& global_ports,
+                                          const PinConstraints& pin_constraints,
                                          const AtomContext& atom_ctx,
                                          const VprNetlistAnnotation& netlist_annotation,
                                          const std::vector<std::string>& clock_port_names,
@ -751,7 +754,12 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
   
    /* Each logical block assumes a single-width port */
    BasicPort input_port(block_name + shared_input_port_postfix, 1); 
+    /* For global ports, use wires; otherwise, use registers*/
+    if (false == port_is_fabric_global_reset_port(global_ports, module_manager, pin_constraints.net_pin(block_name))) { 
      fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl;
+    } else {
+      fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, input_port) << ";" << std::endl;
+    }
  }

  /* Add an empty line as splitter */
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@ -15,6 +15,8 @@
 #include "fabric_global_port_info.h"
 #include "pin_constraints.h"
 #include "simulation_setting.h"
+#include "fabric_global_port_info.h"
+#include "pin_constraints.h"

 /********************************************************************
 * Function declaration
@ -98,6 +100,9 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
                                            const bool& no_self_checking);

 void print_verilog_testbench_shared_ports(std::fstream& fp,
+                                          const ModuleManager& module_manager,
+                                          const FabricGlobalPortInfo& global_ports,
+                                          const PinConstraints& pin_constraints,
                                          const AtomContext& atom_ctx,
                                          const VprNetlistAnnotation& netlist_annotation,
                                          const std::vector<std::string>& clock_port_names,
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@ -407,10 +407,15 @@ void print_verilog_top_testbench_global_reset_ports_stimuli(std::fstream& fp,
        /* - If constrained to a given net in the benchmark, we connect the global pin to the net */
        if ( (false == pin_constraints.unconstrained_net(constrained_net_name))
          && (false == pin_constraints.unmapped_net(constrained_net_name))) {
-          BasicPort benchmark_pin(constrained_net_name, 1);
+          BasicPort benchmark_pin(constrained_net_name + std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), 1);
+          /* Polarity of some input may have to be inverted, as defined in pin constraints
+           * For example, the reset signal of the benchmark is active low 
+           * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted)
+           * However, to ensure correct stimuli to the benchmark, we have to invert the signal
+           */
          print_verilog_wire_connection(fp, module_global_pin,
                                        benchmark_pin,
-                                        false);
+                                        PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(constrained_net_name));
          continue; /* Finish the net assignment for this reset pin */
        }
      }
@ -693,6 +698,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
                                       const AtomContext& atom_ctx,
                                       const VprNetlistAnnotation& netlist_annotation,
                                       const std::vector<std::string>& clock_port_names,
+                                       const FabricGlobalPortInfo& global_ports,
                                       const PinConstraints& pin_constraints,
                                       const SimulationSetting& simulation_parameters,
                                       const ConfigProtocol& config_protocol,
@ -798,7 +804,10 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
                                                    simulation_parameters,
                                                    op_clock_port);

-  print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
+  std::vector<std::string> global_port_names;
+  print_verilog_testbench_shared_ports(fp, 
+                                       module_manager, global_ports, pin_constraints,
+                                       atom_ctx, netlist_annotation,
                                       clock_port_names,
                                       std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
                                       std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
@ -1967,6 +1976,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
  print_verilog_top_testbench_ports(fp, module_manager, top_module,
                                    atom_ctx, netlist_annotation,
                                    clock_port_names,
+                                    global_ports,
                                    pin_constraints,
                                    simulation_parameters, config_protocol,
                                    circuit_name,
--- a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga
@ -0,0 +1,74 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} ${OPENFPGA_FULL_TESTBENCH_OPTIONS}
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
--- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh
@ -7,7 +7,9 @@ PYTHON_EXEC=python3.8
 # OpenFPGA Shell with VPR8
 ##############################################
 echo -e "Micro benchmark regression tests";
-run-task benchmark_sweep/counter --debug --show_thread_logs
+run-task benchmark_sweep/counter8 --debug --show_thread_logs
+run-task benchmark_sweep/counter8_full_testbench --debug --show_thread_logs
+run-task benchmark_sweep/counter128 --debug --show_thread_logs
 run-task benchmark_sweep/mac_units --debug --show_thread_logs

 # Verify MCNC big20 benchmark suite with ModelSim
--- a/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/counter128/config/task.conf
@ -27,10 +27,8 @@ vpr_route_chan_width=50
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml

 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v
-bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v

 [SYNTHESIS_PARAM]
 # Yosys script parameters
@ -46,8 +44,6 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df

 bench0_top = counter
 bench1_top = counter
-bench2_top = counter
-bench3_top = counter

 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 #end_flow_with_test=
--- a/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_reset.xml
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_reset.xml
@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="reset"/>
+</pin_constraints>
+
--- a/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_resetb.xml
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_resetb.xml
@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="resetb" default_value="1"/>
+</pin_constraints>
+
--- a/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_rst.xml
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_rst.xml
@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="rst_counter"/>
+</pin_constraints>
+
--- a/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf
@ -0,0 +1,54 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 5*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
+bench_yosys_bram_map_rules_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
+bench_yosys_bram_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
+bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
+bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = counter
+bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_rst.xml
+
+bench1_top = counter
+bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+
+bench2_top = counter
+bench2_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
--- a/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/pin_constraints_reset.xml
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/pin_constraints_reset.xml
@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="reset"/>
+</pin_constraints>
+
--- a/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/pin_constraints_resetb.xml
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/pin_constraints_resetb.xml
@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="resetb" default_value="1"/>
+</pin_constraints>
+
--- a/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/pin_constraints_rst.xml
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/pin_constraints_rst.xml
@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="rst_counter"/>
+</pin_constraints>
+
--- a/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/task.conf
@ -0,0 +1,55 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 5*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_full_testbench_options=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
+bench_yosys_bram_map_rules_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
+bench_yosys_bram_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
+bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
+bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = counter
+bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_rst.xml
+
+bench1_top = counter
+bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+
+bench2_top = counter
+bench2_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=