From 1e7cca8cebfb4991885863c0463c2f5ffd2f4fc9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 2 Jul 2024 11:52:30 -0700
Subject: [PATCH] [arch] code format

---
 openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
index ad21e6f59..013466e5c 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
@@ -108,8 +108,8 @@
           <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
         </fc>
         <pinlocations pattern="custom">
-          <loc side="left"></loc>
-          <loc side="top"></loc>
+          <loc side="left"/>
+          <loc side="top"/>
           <loc side="right">clb.reset clb.clk clb.O[4:7] clb.I[6:11]</loc>
           <loc side="bottom">clb.O[0:3] clb.I[0:5]</loc>
         </pinlocations>