From 1e6955aaa4ff8a6e68067da01e48a5a6146abd1e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 4 Jul 2020 19:13:28 -0600 Subject: [PATCH] rename arch directory to be clear for its usage --- openfpga_flow/tasks/behavioral_verilog/config/task.conf | 2 +- openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf | 2 +- openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf | 2 +- openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf | 2 +- openfpga_flow/tasks/bram/dpram16k/config/task.conf | 2 +- openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf | 2 +- openfpga_flow/tasks/compilation_verification/config/task.conf | 2 +- openfpga_flow/tasks/duplicated_grid_pin/config/task.conf | 2 +- openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf | 2 +- .../tasks/fabric_chain/register_chain/config/task.conf | 2 +- openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf | 2 +- .../tasks/fabric_key/generate_random_key/config/task.conf | 2 +- .../tasks/fabric_key/generate_vanilla_key/config/task.conf | 2 +- .../tasks/fabric_key/load_external_key/config/task.conf | 2 +- openfpga_flow/tasks/fixed_simulation_settings/config/task.conf | 2 +- openfpga_flow/tasks/flatten_routing/config/task.conf | 2 +- .../tasks/full_testbench/configuration_chain/config/task.conf | 2 +- .../tasks/full_testbench/configuration_frame/config/task.conf | 2 +- .../full_testbench/fast_configuration_frame/config/task.conf | 2 +- .../tasks/full_testbench/fast_memory_bank/config/task.conf | 2 +- .../tasks/full_testbench/flatten_memory/config/task.conf | 2 +- openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf | 2 +- openfpga_flow/tasks/generate_bitstream/config/task.conf | 2 +- openfpga_flow/tasks/generate_fabric/config/task.conf | 2 +- openfpga_flow/tasks/generate_testbench/config/task.conf | 2 +- openfpga_flow/tasks/hard_adder/config/task.conf | 2 +- openfpga_flow/tasks/implicit_verilog/config/task.conf | 2 +- openfpga_flow/tasks/io/aib/config/task.conf | 2 +- openfpga_flow/tasks/io/multi_io_capacity/config/task.conf | 2 +- openfpga_flow/tasks/io/reduced_io/config/task.conf | 2 +- openfpga_flow/tasks/lut_design/frac_lut/config/task.conf | 2 +- .../tasks/lut_design/intermediate_buffer/config/task.conf | 2 +- openfpga_flow/tasks/lut_design/single_mode/config/task.conf | 2 +- openfpga_flow/tasks/mcnc_big20/config/task.conf | 2 +- openfpga_flow/tasks/mux_design/local_encoder/config/task.conf | 2 +- openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf | 2 +- openfpga_flow/tasks/mux_design/tree_structure/config/task.conf | 2 +- openfpga_flow/tasks/ncounter/config/task.conf | 2 +- .../preconfig_testbench/configuration_chain/config/task.conf | 2 +- .../preconfig_testbench/configuration_frame/config/task.conf | 2 +- .../tasks/preconfig_testbench/flatten_memory/config/task.conf | 2 +- .../tasks/preconfig_testbench/memory_bank/config/task.conf | 2 +- openfpga_flow/tasks/sdc_time_unit/config/task.conf | 2 +- openfpga_flow/tasks/spypad/config/task.conf | 2 +- openfpga_flow/tasks/untileable/config/task.conf | 2 +- openfpga_flow/{arch/vpr_only_templates => vpr_arch}/README.md | 0 .../vpr_only_templates => vpr_arch}/k4_N4_tileable_40nm.xml | 0 .../{arch/vpr_only_templates => vpr_arch}/k6_N10_40nm.xml | 0 .../vpr_only_templates => vpr_arch}/k6_N10_tileable_40nm.xml | 0 .../{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_40nm.xml | 0 .../k6_frac_N10_adder_chain_40nm.xml | 0 .../k6_frac_N10_adder_chain_mem16K_40nm.xml | 0 .../k6_frac_N10_tileable_40nm.xml | 0 .../k6_frac_N10_tileable_adder_chain_40nm.xml | 0 .../k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml | 0 .../k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml | 0 ...c_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml | 0 .../k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml | 0 .../k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml | 0 .../k6_frac_N10_tileable_adder_register_chain_40nm.xml | 0 .../k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml | 0 ...frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml | 0 ...0_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml | 0 ...0_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml | 0 ...6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml | 0 65 files changed, 45 insertions(+), 45 deletions(-) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/README.md (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k4_N4_tileable_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_N10_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_N10_tileable_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_adder_chain_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_adder_chain_mem16K_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_chain_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_register_chain_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml (100%) rename openfpga_flow/{arch/vpr_only_templates => vpr_arch}/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml (100%) diff --git a/openfpga_flow/tasks/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/behavioral_verilog/config/task.conf index 2a904e42e..88dcf68a2 100644 --- a/openfpga_flow/tasks/behavioral_verilog/config/task.conf +++ b/openfpga_flow/tasks/behavioral_verilog/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index 1f67896ba..a35635cf4 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif diff --git a/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf index f44e44b38..4b731c716 100644 --- a/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/fsm/FSM_top.blif diff --git a/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf index 831510c48..3b3fa43b2 100644 --- a/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.blif diff --git a/openfpga_flow/tasks/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/bram/dpram16k/config/task.conf index 266de6a39..decb20187 100644 --- a/openfpga_flow/tasks/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/bram/dpram16k/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf index 0c681a8ba..04cf52c9f 100644 --- a/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/compilation_verification/config/task.conf b/openfpga_flow/tasks/compilation_verification/config/task.conf index e2c4749fe..dca01bcfd 100644 --- a/openfpga_flow/tasks/compilation_verification/config/task.conf +++ b/openfpga_flow/tasks/compilation_verification/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf index bc644f527..68079ff8c 100644 --- a/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf +++ b/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf index 4c7e8c562..a396bb03f 100644 --- a/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf +++ b/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf index 721e4fe4b..b0eba5ea8 100644 --- a/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf +++ b/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf index 893510c6b..0b026ac5c 100644 --- a/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf +++ b/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf index e32ed3691..25cfc09ac 100644 --- a/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf +++ b/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf index 3878b0a66..a1c85ee59 100644 --- a/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf +++ b/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf index 4be35916c..975cfd8f4 100644 --- a/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf +++ b/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf index 10904ffad..333cb6d63 100644 --- a/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf +++ b/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/flatten_routing/config/task.conf b/openfpga_flow/tasks/flatten_routing/config/task.conf index 351ba7d15..bcee2e245 100644 --- a/openfpga_flow/tasks/flatten_routing/config/task.conf +++ b/openfpga_flow/tasks/flatten_routing/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf index 8aa859ce2..9b21a6a26 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf index c1510b55e..dab7a9e3c 100644 --- a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf index 26f9532ba..5ef4a8a2a 100644 --- a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf index a07b68254..feb5f4372 100644 --- a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf index 9fe9eea6e..45946b434 100644 --- a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf index 508935fa0..94957ac84 100644 --- a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/generate_bitstream/config/task.conf b/openfpga_flow/tasks/generate_bitstream/config/task.conf index 4c12ab08b..e684dd543 100644 --- a/openfpga_flow/tasks/generate_bitstream/config/task.conf +++ b/openfpga_flow/tasks/generate_bitstream/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/generate_fabric/config/task.conf b/openfpga_flow/tasks/generate_fabric/config/task.conf index edfe6181f..0da9d6248 100644 --- a/openfpga_flow/tasks/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/generate_fabric/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/generate_testbench/config/task.conf b/openfpga_flow/tasks/generate_testbench/config/task.conf index 0892e9364..011aa823c 100644 --- a/openfpga_flow/tasks/generate_testbench/config/task.conf +++ b/openfpga_flow/tasks/generate_testbench/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/hard_adder/config/task.conf b/openfpga_flow/tasks/hard_adder/config/task.conf index 899fc9aab..6f4efcd1e 100644 --- a/openfpga_flow/tasks/hard_adder/config/task.conf +++ b/openfpga_flow/tasks/hard_adder/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/implicit_verilog/config/task.conf b/openfpga_flow/tasks/implicit_verilog/config/task.conf index 00447677c..5ebdd49a7 100644 --- a/openfpga_flow/tasks/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/implicit_verilog/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif diff --git a/openfpga_flow/tasks/io/aib/config/task.conf b/openfpga_flow/tasks/io/aib/config/task.conf index 27f428808..17367750a 100644 --- a/openfpga_flow/tasks/io/aib/config/task.conf +++ b/openfpga_flow/tasks/io/aib/config/task.conf @@ -31,7 +31,7 @@ external_fabric_key_file= #################################### [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf index 18316d71d..96a4d348e 100644 --- a/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf +++ b/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/io/reduced_io/config/task.conf b/openfpga_flow/tasks/io/reduced_io/config/task.conf index 92e2d8403..50671bfd9 100644 --- a/openfpga_flow/tasks/io/reduced_io/config/task.conf +++ b/openfpga_flow/tasks/io/reduced_io/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf index e19f2d087..08a28be87 100644 --- a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] # diff --git a/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf index 8529ef721..7e8e55be9 100644 --- a/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf +++ b/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml [BENCHMARKS] # diff --git a/openfpga_flow/tasks/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/lut_design/single_mode/config/task.conf index 514ccfa09..2f12d2377 100644 --- a/openfpga_flow/tasks/lut_design/single_mode/config/task.conf +++ b/openfpga_flow/tasks/lut_design/single_mode/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index 45f359d7d..620e575bc 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif diff --git a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf index de42dcc89..a9ddefc19 100644 --- a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf +++ b/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf index c338543fc..426bb8884 100644 --- a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf index b115aa4b3..9c63bfdbd 100644 --- a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/ncounter/config/task.conf b/openfpga_flow/tasks/ncounter/config/task.conf index e33bddde7..33ed59e53 100644 --- a/openfpga_flow/tasks/ncounter/config/task.conf +++ b/openfpga_flow/tasks/ncounter/config/task.conf @@ -19,7 +19,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml [BENCHMARKS] bench0=/var/tmp/AA_SC/ncounter_task/Ncounter.blif diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf index 257b77576..53354162b 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf index e2c4749fe..dca01bcfd 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf index 8ef21c6ae..a413be671 100644 --- a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf index 367521841..bb9f7c11f 100644 --- a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/sdc_time_unit/config/task.conf index 4e3886f9e..c1d780690 100644 --- a/openfpga_flow/tasks/sdc_time_unit/config/task.conf +++ b/openfpga_flow/tasks/sdc_time_unit/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/spypad/config/task.conf b/openfpga_flow/tasks/spypad/config/task.conf index dd50eacd8..51197d1f7 100644 --- a/openfpga_flow/tasks/spypad/config/task.conf +++ b/openfpga_flow/tasks/spypad/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/untileable/config/task.conf b/openfpga_flow/tasks/untileable/config/task.conf index 52d05da7b..cdc1769b1 100644 --- a/openfpga_flow/tasks/untileable/config/task.conf +++ b/openfpga_flow/tasks/untileable/config/task.conf @@ -20,7 +20,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/arch/vpr_only_templates/README.md b/openfpga_flow/vpr_arch/README.md similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/README.md rename to openfpga_flow/vpr_arch/README.md diff --git a/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml rename to openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml rename to openfpga_flow/vpr_arch/k6_N10_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml rename to openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_mem16K_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml similarity index 100% rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml