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[core] code format

This commit is contained in:
tangxifan 2023-09-18 15:35:13 -07:00
parent 110301a2e4
commit 1daabb990e
6 changed files with 81 additions and 77 deletions
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18
openfpga/src/fabric/build_device_module.cpp
View File

@ -120,12 +120,13 @@ int build_device_module_graph(
return status;
}
/* Build the modules */
build_tile_modules(
module_manager, decoder_lib, openfpga_ctx.fabric_tile(),
vpr_device_ctx.grid, openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
openfpga_ctx.arch().circuit_lib, sram_model,
openfpga_ctx.arch().config_protocol.type(), name_module_using_index, frame_view, verbose);
build_tile_modules(module_manager, decoder_lib, openfpga_ctx.fabric_tile(),
vpr_device_ctx.grid,
openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
openfpga_ctx.arch().circuit_lib, sram_model,
openfpga_ctx.arch().config_protocol.type(),
name_module_using_index, frame_view, verbose);
}
/* Build FPGA fabric top-level module */
@ -136,8 +137,9 @@ int build_device_module_graph(
openfpga_ctx.arch().tile_annotations, vpr_device_ctx.rr_graph,
openfpga_ctx.device_rr_gsb(), openfpga_ctx.tile_direct(),
openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol,
sram_model, fabric_tile, name_module_using_index, frame_view, compress_routing, duplicate_grid_pin,
fabric_key, generate_random_fabric_key, group_config_block, verbose);
sram_model, fabric_tile, name_module_using_index, frame_view,
compress_routing, duplicate_grid_pin, fabric_key,
generate_random_fabric_key, group_config_block, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;

77
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -66,10 +66,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb(
const RRGSB& rr_gsb, const FabricTile& fabric_tile,
const FabricTileId& fabric_tile_id, const std::vector<size_t>& pb_instances,
const std::vector<size_t>& sb_instances, const size_t& isb,
const bool& compact_routing_hierarchy,
const bool& name_module_using_index,
const bool& frame_view,
const bool& verbose) {
const bool& compact_routing_hierarchy, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
/* Skip those Switch blocks that do not exist */
if (false == rr_gsb.is_sb_exist(rr_graph)) {
return CMD_EXEC_SUCCESS;
@ -202,13 +200,15 @@ static int build_tile_module_port_and_nets_between_sb_and_pb(
} else {
/* Create a port on the tile module and create the net if required.
* Create a proper name to avoid naming conflicts */
std::string temp_sb_module_name = generate_switch_block_module_name(fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
std::string temp_sb_module_name = generate_switch_block_module_name(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
if (name_module_using_index) {
temp_sb_module_name = generate_switch_block_module_name_using_index(device_rr_gsb.get_sb_unique_module_index(fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
}
temp_sb_module_name = generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
}
src_grid_port.set_name(generate_tile_module_port_name(
temp_sb_module_name,
sink_sb_port.get_name()));
temp_sb_module_name, sink_sb_port.get_name()));
ModulePortId src_tile_port_id = module_manager.add_port(
tile_module, src_grid_port,
ModuleManager::e_module_port_type::MODULE_INPUT_PORT);
@ -301,8 +301,8 @@ static int build_tile_module_port_and_nets_between_cb_and_pb(
const std::vector<size_t>& pb_instances,
const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
const size_t& icb, const bool& compact_routing_hierarchy,
const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
const bool& name_module_using_index, const bool& frame_view,
const bool& verbose) {
size_t cb_instance = cb_instances.at(cb_type)[icb];
/* We could have two different coordinators, one is the instance, the other is
* the module */
@ -435,7 +435,10 @@ static int build_tile_module_port_and_nets_between_cb_and_pb(
generate_connection_block_module_name(
cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_tile = generate_connection_block_module_name_using_index(cb_type, device_rr_gsb.get_cb_unique_module_index(cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
cb_instance_name_in_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
}
src_cb_port.set_name(generate_tile_module_port_name(
cb_instance_name_in_tile, src_cb_port.get_name()));
@ -512,10 +515,8 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
const FabricTileId& fabric_tile_id,
const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
const std::vector<size_t>& sb_instances, const size_t& isb,
const bool& compact_routing_hierarchy,
const bool& name_module_using_index,
const bool& frame_view,
const bool& verbose) {
const bool& compact_routing_hierarchy, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
size_t sb_instance = sb_instances[isb];
/* We could have two different coordinators, one is the instance, the other is
* the module */
@ -699,13 +700,15 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
module_manager.find_module_port(sb_module_id, chan_input_port_name);
BasicPort chan_input_port =
module_manager.module_port(sb_module_id, sb_chan_input_port_id);
std::string temp_sb_module_name = generate_switch_block_module_name(fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
std::string temp_sb_module_name = generate_switch_block_module_name(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
if (name_module_using_index) {
temp_sb_module_name = generate_switch_block_module_name_using_index(device_rr_gsb.get_sb_unique_module_index(fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
temp_sb_module_name = generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
}
chan_input_port.set_name(generate_tile_module_port_name(
temp_sb_module_name,
chan_input_port.get_name()));
temp_sb_module_name, chan_input_port.get_name()));
ModulePortId tile_chan_input_port_id = module_manager.add_port(
tile_module, chan_input_port,
ModuleManager::e_module_port_type::MODULE_INPUT_PORT);
@ -736,8 +739,7 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
BasicPort chan_output_port =
module_manager.module_port(sb_module_id, sb_chan_output_port_id);
chan_output_port.set_name(generate_tile_module_port_name(
temp_sb_module_name,
chan_output_port.get_name()));
temp_sb_module_name, chan_output_port.get_name()));
ModulePortId tile_chan_output_port_id = module_manager.add_port(
tile_module, chan_output_port,
ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT);
@ -877,8 +879,8 @@ static int build_tile_module_ports_from_cb(
const t_rr_type& cb_type,
const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
const size_t& icb, const bool& compact_routing_hierarchy,
const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
const bool& name_module_using_index, const bool& frame_view,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
size_t cb_instance = cb_instances.at(cb_type)[icb];
@ -922,8 +924,10 @@ static int build_tile_module_ports_from_cb(
std::string cb_instance_name_in_tile = generate_connection_block_module_name(
cb_type, unique_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_tile = generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(cb_type, unique_rr_gsb.get_cb_coordinate(cb_type)));
cb_instance_name_in_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, unique_rr_gsb.get_cb_coordinate(cb_type)));
}
vtr::Point<size_t> tile_coord =
fabric_tile.tile_coordinate(curr_fabric_tile_id);
@ -1008,8 +1012,7 @@ static int build_tile_port_and_nets_from_pb(
const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph,
const vtr::Point<size_t>& pb_coord, const std::vector<size_t>& pb_instances,
const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
const size_t& ipb,
const bool& frame_view, const bool& verbose) {
const size_t& ipb, const bool& frame_view, const bool& verbose) {
size_t pb_instance = pb_instances[ipb];
t_physical_tile_type_ptr phy_tile = grids.get_physical_type(
t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer));
@ -1199,10 +1202,8 @@ static int build_tile_module_ports_and_nets(
const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id,
const std::vector<size_t>& pb_instances,
const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
const std::vector<size_t>& sb_instances,
const bool& name_module_using_index,
const bool& frame_view,
const bool& verbose) {
const std::vector<size_t>& sb_instances, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
int status_code = CMD_EXEC_SUCCESS;
/* Get the submodule of Switch blocks one by one, build connections between sb
@ -1215,7 +1216,8 @@ static int build_tile_module_ports_and_nets(
status_code = build_tile_module_port_and_nets_between_sb_and_pb(
module_manager, tile_module, grids, layer, vpr_device_annotation,
device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id,
pb_instances, sb_instances, isb, true, name_module_using_index, frame_view, verbose);
pb_instances, sb_instances, isb, true, name_module_using_index,
frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1232,7 +1234,8 @@ static int build_tile_module_ports_and_nets(
status_code = build_tile_module_port_and_nets_between_cb_and_pb(
module_manager, tile_module, grids, layer, vpr_device_annotation,
device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id,
cb_type, pb_instances, cb_instances, icb, true, name_module_using_index, frame_view, verbose);
cb_type, pb_instances, cb_instances, icb, true, name_module_using_index,
frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1281,7 +1284,8 @@ static int build_tile_module_ports_and_nets(
/* Build any ports missing from connection blocks */
status_code = build_tile_module_ports_from_cb(
module_manager, tile_module, device_rr_gsb, rr_gsb, fabric_tile,
fabric_tile_id, cb_type, cb_instances, icb, true, name_module_using_index, frame_view, verbose);
fabric_tile_id, cb_type, cb_instances, icb, true,
name_module_using_index, frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1307,8 +1311,7 @@ static int build_tile_module(
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index,
const bool& frame_view,
const bool& name_module_using_index, const bool& frame_view,
const bool& verbose) {
int status_code = CMD_EXEC_SUCCESS;

13
openfpga/src/fabric/build_top_module.cpp
View File

@ -55,11 +55,10 @@ int build_top_module(
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricTile& fabric_tile,
const bool& name_module_using_index,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& generate_random_fabric_key, const bool& group_config_block,
const bool& verbose) {
const bool& name_module_using_index, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const bool& generate_random_fabric_key,
const bool& group_config_block, const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
int status = CMD_EXEC_SUCCESS;
@ -87,8 +86,8 @@ int build_top_module(
module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk,
rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile,
config_protocol, sram_model, fabric_key, group_config_block, name_module_using_index, frame_view,
verbose);
config_protocol, sram_model, fabric_key, group_config_block,
name_module_using_index, frame_view, verbose);
}
if (status != CMD_EXEC_SUCCESS) {

9
openfpga/src/fabric/build_top_module.h
View File

@ -42,11 +42,10 @@ int build_top_module(
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricTile& fabric_tile,
const bool& name_module_using_index,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& generate_random_fabric_key, const bool& group_config_block,
const bool& verbose);
const bool& name_module_using_index, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const bool& generate_random_fabric_key,
const bool& group_config_block, const bool& verbose);
} /* end namespace openfpga */

38
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -290,8 +290,7 @@ static int build_top_module_tile_nets_between_sb_and_pb(
const RRGSB& rr_gsb, const FabricTile& fabric_tile,
const FabricTileId& curr_fabric_tile_id,
const size_t& sb_idx_in_curr_fabric_tile,
const bool& compact_routing_hierarchy,
const bool& name_module_using_index,
const bool& compact_routing_hierarchy, const bool& name_module_using_index,
const bool& verbose) {
/* Skip those Switch blocks that do not exist */
if (false == rr_gsb.is_sb_exist(rr_graph)) {
@ -306,7 +305,9 @@ static int build_top_module_tile_nets_between_sb_and_pb(
std::string sink_sb_instance_name_in_unique_tile =
generate_switch_block_module_name(sink_sb_coord_in_unique_tile);
if (name_module_using_index) {
sink_sb_instance_name_in_unique_tile = generate_switch_block_module_name_using_index(device_rr_gsb.get_sb_unique_module_index(sink_sb_coord_in_unique_tile));
sink_sb_instance_name_in_unique_tile =
generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(sink_sb_coord_in_unique_tile));
}
/* We could have two different coordinators, one is the instance, the other is
@ -531,8 +532,7 @@ static int build_top_module_tile_nets_between_cb_and_pb(
const RRGSB& rr_gsb, const FabricTile& fabric_tile,
const FabricTileId& curr_fabric_tile_id, const t_rr_type& cb_type,
const size_t& cb_idx_in_curr_fabric_tile,
const bool& compact_routing_hierarchy,
const bool& name_module_using_index,
const bool& compact_routing_hierarchy, const bool& name_module_using_index,
const bool& verbose) {
vtr::Point<size_t> src_tile_coord =
fabric_tile.tile_coordinate(curr_fabric_tile_id);
@ -545,8 +545,10 @@ static int build_top_module_tile_nets_between_cb_and_pb(
generate_connection_block_module_name(
cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
src_cb_instance_name_in_unique_tile = generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
src_cb_instance_name_in_unique_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
}
/* We could have two different coordinators, one is the instance, the other is
@ -731,8 +733,7 @@ static int build_top_module_tile_nets_between_sb_and_cb(
const RRGraphView& rr_graph, const RRGSB& rr_gsb,
const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
const size_t& sb_idx_in_curr_fabric_tile,
const bool& compact_routing_hierarchy,
const bool& name_module_using_index,
const bool& compact_routing_hierarchy, const bool& name_module_using_index,
const bool& verbose) {
/* We could have two different coordinators, one is the instance, the other is
* the module */
@ -748,7 +749,9 @@ static int build_top_module_tile_nets_between_sb_and_cb(
std::string sb_instance_name_in_unique_tile =
generate_switch_block_module_name(sb_coord_in_unique_tile);
if (name_module_using_index) {
sb_instance_name_in_unique_tile = generate_switch_block_module_name_using_index(device_rr_gsb.get_sb_unique_module_index(sb_coord_in_unique_tile));
sb_instance_name_in_unique_tile =
generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(sb_coord_in_unique_tile));
}
/* Skip those Switch blocks that do not exist */
@ -854,7 +857,8 @@ static int build_top_module_tile_nets_between_sb_and_cb(
if (name_module_using_index) {
cb_instance_name_in_unique_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type)));
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type)));
}
std::string cb_tile_module_name =
generate_tile_module_name(cb_unique_tile_coord);
@ -976,8 +980,7 @@ static int add_top_module_nets_around_one_tile(
const vtr::Matrix<size_t>& tile_instance_ids,
const RRGraphView& rr_graph_view, const DeviceRRGSB& device_rr_gsb,
const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
const bool& name_module_using_index,
const bool& verbose) {
const bool& name_module_using_index, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
/* Find the module name for this type of tile */
@ -1057,8 +1060,7 @@ static int add_top_module_nets_connect_tiles(
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const vtr::Matrix<size_t>& tile_instance_ids, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile,
const bool& name_module_using_index,
const bool& verbose) {
const bool& name_module_using_index, const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Add module nets between tiles");
int status = CMD_EXEC_SUCCESS;
@ -1897,8 +1899,7 @@ int build_top_module_tile_child_instances(
const TileDirect& tile_direct, const ArchDirect& arch_direct,
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricKey& fabric_key,
const bool& group_config_block,
const bool& name_module_using_index,
const bool& group_config_block, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
vtr::Matrix<size_t> tile_instance_ids;
@ -1919,7 +1920,8 @@ int build_top_module_tile_child_instances(
/* Regular nets between tiles */
status = add_top_module_nets_connect_tiles(
module_manager, top_module, vpr_device_annotation, grids,
tile_instance_ids, rr_graph, device_rr_gsb, fabric_tile, name_module_using_index, verbose);
tile_instance_ids, rr_graph, device_rr_gsb, fabric_tile,
name_module_using_index, verbose);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}

3
openfpga/src/fabric/build_top_module_child_tile_instance.h
View File

@ -43,8 +43,7 @@ int build_top_module_tile_child_instances(
const TileDirect& tile_direct, const ArchDirect& arch_direct,
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricKey& fabric_key,
const bool& group_config_block,
const bool& name_module_using_index,
const bool& group_config_block, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose);
} /* end namespace openfpga */