minor format fix on documentation

docs/source/arch_lang/annotate_vpr_arch.rst

@@ -13,7 +13,7 @@ Configuration Protocol
     <organization type="<string>" circuit_model_name="<string>"/>
   </configuration_protocol>
 
- - ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits.
+- ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits.
 
 :numref:`fig_sram` illustrates an example where a memory organization using memory decoders and 6-transistor SRAMs.
 
@@ -43,7 +43,7 @@ Here is an example:
     <switch type="mux" name="<string>" circuit_model_name="<string>"/>
   </switch_block>
 
- - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
+- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
 
 
 Connection Blocks
@@ -59,7 +59,7 @@ Here is the example:
     <switch type="ipin_cblock" name="<string>" circuit_model_name="<string>"/>
   </connection_block>
 
- - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
+- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
 
 Channel Wire Segments
 ~~~~~~~~~~~~~~~~~~~~~
@@ -72,7 +72,7 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
     <segment name="<string>" circuit_model_name="<string>"/>
   </segmentlist>
 
- - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``chan_wire`` defined in :ref:`circuit_library`.
+- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``chan_wire`` defined in :ref:`circuit_library`.
 
 Primitive Blocks inside Multi-mode Configurable Logic Blocks
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

docs/source/fpga_spice/index.rst

@@ -1,5 +1,8 @@
 FPGA-SPICE
 ----------
+
+.. warning:: FPGA-SPICE has not been integrated to VPR8 version yet. Please the following tool guide is for VPR7 version now
+
 .. _fpga_spice:
    FPGA-SPICE
  

docs/source/fpga_verilog/index.rst

@@ -1,5 +1,6 @@
 FPGA-Verilog
 ------------
+
 .. _fpga_verilog:
    FPGA-Verilog
  

docs/source/openfpga_shell/openfpga_commands.rst

@@ -57,7 +57,7 @@ Setup OpenFPGA
   Check and correct any naming conflicts in the BLIF netlist
   This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
 
-  .. note:: This command may be deprecated in future when merged to VPR upstream
+  .. warning:: This command may be deprecated in future when it is merged to VPR upstream
   
   - ``--fix`` Apply fix-up to the names that violate the syntax
 
@@ -68,7 +68,7 @@ Setup OpenFPGA
   Apply fix-up to clustering nets based on routing results
   This is strongly recommended. Otherwise, the bitstream generation may be wrong
 
-  .. note:: This command may be deprecated in future when merged to VPR upstream
+  .. warning:: This command may be deprecated in future when it is merged to VPR upstream
   
   - ``--verbose`` Show verbose log
    
@@ -76,13 +76,13 @@ Setup OpenFPGA
 
   Apply fix-up to Look-Up Table truth tables based on packing results
 
-  .. note:: This command may be deprecated in future when merged to VPR upstream
+  .. warning:: This command may be deprecated in future when it is merged to VPR upstream
 
   - ``--verbose`` Show verbose log
   
 .. option:: build_fabric
 
-  Build the module graph. This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
+  Build the module graph.
 
   - ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
   
@@ -90,6 +90,9 @@ Setup OpenFPGA
 
   - ``--verbose`` Show verbose log
 
+  .. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
+
+  
 FPGA-Bitstream
 ~~~~~~~~~~~~~~