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minor format fix on documentation

This commit is contained in:
tangxifan 2020-03-11 10:22:30 -06:00
parent b941ac8a4a
commit 1d766d2a70
4 changed files with 15 additions and 8 deletions
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3
docs/source/fpga_spice/index.rst
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@ -1,5 +1,8 @@
FPGA-SPICE
----------
.. warning:: FPGA-SPICE has not been integrated to VPR8 version yet. Please the following tool guide is for VPR7 version now
.. _fpga_spice:
FPGA-SPICE

1
docs/source/fpga_verilog/index.rst
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@ -1,5 +1,6 @@
FPGA-Verilog
------------
.. _fpga_verilog:
FPGA-Verilog

11
docs/source/openfpga_shell/openfpga_commands.rst
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@ -57,7 +57,7 @@ Setup OpenFPGA
Check and correct any naming conflicts in the BLIF netlist
This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
.. note:: This command may be deprecated in future when merged to VPR upstream
.. warning:: This command may be deprecated in future when it is merged to VPR upstream
- ``--fix`` Apply fix-up to the names that violate the syntax
@ -68,7 +68,7 @@ Setup OpenFPGA
Apply fix-up to clustering nets based on routing results
This is strongly recommended. Otherwise, the bitstream generation may be wrong
.. note:: This command may be deprecated in future when merged to VPR upstream
.. warning:: This command may be deprecated in future when it is merged to VPR upstream
- ``--verbose`` Show verbose log
@ -76,13 +76,13 @@ Setup OpenFPGA
Apply fix-up to Look-Up Table truth tables based on packing results
.. note:: This command may be deprecated in future when merged to VPR upstream
.. warning:: This command may be deprecated in future when it is merged to VPR upstream
- ``--verbose`` Show verbose log
.. option:: build_fabric
Build the module graph. This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
Build the module graph.
- ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
@ -90,6 +90,9 @@ Setup OpenFPGA
- ``--verbose`` Show verbose log
.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
FPGA-Bitstream
~~~~~~~~~~~~~~