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minor format fix on documentation

This commit is contained in:
tangxifan 2020-03-11 10:22:30 -06:00
parent b941ac8a4a
commit 1d766d2a70
4 changed files with 15 additions and 8 deletions
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8
docs/source/arch_lang/annotate_vpr_arch.rst
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@ -13,7 +13,7 @@ Configuration Protocol
<organization type="<string>" circuit_model_name="<string>"/> <organization type="<string>" circuit_model_name="<string>"/>
</configuration_protocol> </configuration_protocol>
- ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits. - ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits.
:numref:`fig_sram` illustrates an example where a memory organization using memory decoders and 6-transistor SRAMs. :numref:`fig_sram` illustrates an example where a memory organization using memory decoders and 6-transistor SRAMs.
@ -43,7 +43,7 @@ Here is an example:
<switch type="mux" name="<string>" circuit_model_name="<string>"/> <switch type="mux" name="<string>" circuit_model_name="<string>"/>
</switch_block> </switch_block>
- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`. - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
Connection Blocks Connection Blocks
@ -59,7 +59,7 @@ Here is the example:
<switch type="ipin_cblock" name="<string>" circuit_model_name="<string>"/> <switch type="ipin_cblock" name="<string>" circuit_model_name="<string>"/>
</connection_block> </connection_block>
- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`. - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
Channel Wire Segments Channel Wire Segments
~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~
@ -72,7 +72,7 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
<segment name="<string>" circuit_model_name="<string>"/> <segment name="<string>" circuit_model_name="<string>"/>
</segmentlist> </segmentlist>
- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``chan_wire`` defined in :ref:`circuit_library`. - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``chan_wire`` defined in :ref:`circuit_library`.
Primitive Blocks inside Multi-mode Configurable Logic Blocks Primitive Blocks inside Multi-mode Configurable Logic Blocks
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

3
docs/source/fpga_spice/index.rst
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@ -1,5 +1,8 @@
FPGA-SPICE FPGA-SPICE
---------- ----------
.. warning:: FPGA-SPICE has not been integrated to VPR8 version yet. Please the following tool guide is for VPR7 version now
.. _fpga_spice: .. _fpga_spice:
FPGA-SPICE FPGA-SPICE

1
docs/source/fpga_verilog/index.rst
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@ -1,5 +1,6 @@
FPGA-Verilog FPGA-Verilog
------------ ------------
.. _fpga_verilog: .. _fpga_verilog:
FPGA-Verilog FPGA-Verilog

11
docs/source/openfpga_shell/openfpga_commands.rst
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@ -57,7 +57,7 @@ Setup OpenFPGA
Check and correct any naming conflicts in the BLIF netlist Check and correct any naming conflicts in the BLIF netlist
This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully. This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
.. note:: This command may be deprecated in future when merged to VPR upstream .. warning:: This command may be deprecated in future when it is merged to VPR upstream
- ``--fix`` Apply fix-up to the names that violate the syntax - ``--fix`` Apply fix-up to the names that violate the syntax
@ -68,7 +68,7 @@ Setup OpenFPGA
Apply fix-up to clustering nets based on routing results Apply fix-up to clustering nets based on routing results
This is strongly recommended. Otherwise, the bitstream generation may be wrong This is strongly recommended. Otherwise, the bitstream generation may be wrong
.. note:: This command may be deprecated in future when merged to VPR upstream .. warning:: This command may be deprecated in future when it is merged to VPR upstream
- ``--verbose`` Show verbose log - ``--verbose`` Show verbose log
@ -76,19 +76,22 @@ Setup OpenFPGA
Apply fix-up to Look-Up Table truth tables based on packing results Apply fix-up to Look-Up Table truth tables based on packing results
.. note:: This command may be deprecated in future when merged to VPR upstream .. warning:: This command may be deprecated in future when it is merged to VPR upstream
- ``--verbose`` Show verbose log - ``--verbose`` Show verbose log
.. option:: build_fabric .. option:: build_fabric
Build the module graph. This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE Build the module graph.
- ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly. - ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
- ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed - ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
- ``--verbose`` Show verbose log - ``--verbose`` Show verbose log
.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
FPGA-Bitstream FPGA-Bitstream
~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~