diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga index cd1eb8683..c3e09b46a 100644 --- a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga @@ -56,7 +56,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping -write_preconfigured_testbench --file . --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --use_relative_path --fabric_netlist_file_path ./SRC/fabric_netlists.v +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --use_relative_path #--fabric_netlist_file_path ./SRC/fabric_netlists.v # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 29a4868ca..0c36338a6 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -842,6 +842,9 @@ def run_netlists_verification(exit_if_fail=True): command += [tb_top_formal] else: command += [tb_top_autochecked] + # TODO: This is NOT flexible!!! We should consider to make the include directory customizable through options + # Add source directory to the include dir + command += ["-I", "./SRC"] run_command("iverilog_verification", "iverilog_output.txt", command) vvp_command = ["vvp", compiled_file]