start developing tileable_rr_graph_builder
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/**********************************************************
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* MIT License
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*
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* Copyright (c) 2018 LNIS - The University of Utah
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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***********************************************************************/
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/************************************************************************
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* Filename: rr_graph_tileable_builder.c
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* Created by: Xifan Tang
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* Change history:
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* +-------------------------------------+
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* | Date | Author | Notes
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* +-------------------------------------+
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* | 2019/06/11 | Xifan Tang | Created
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* +-------------------------------------+
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***********************************************************************/
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/************************************************************************
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* This file contains a builder for the complex rr_graph data structure
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* Different from VPR rr_graph builders, this builder aims to create a
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* highly regular rr_graph, where each Connection Block (CB), Switch
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* Block (SB) is the same (except for those on the borders). Thus, the
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* rr_graph is called tileable, which brings significant advantage in
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* producing large FPGA fabrics.
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***********************************************************************/
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#include <stdio.h>
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#include <assert.h>
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#include <string.h>
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#include "vpr_types.h"
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#include "globals.h"
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#include "vpr_utils.h"
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#include "rr_graph_util.h"
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#include "rr_graph.h"
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#include "rr_graph2.h"
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#include "route_common.h"
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#include "fpga_x2p_types.h"
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#include "rr_graph_tileable_builder.h"
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/************************************************************************
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* Main function of this file
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* Builder for a detailed uni-directional tileable rr_graph
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* Global graph is not supported here, the VPR rr_graph generator can be used
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* It follows the procedures to complete the rr_graph generation
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* 1. Assign the segments for each routing channel,
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* To be specific, for each routing track, we assign a routing segment.
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* The assignment is subject to users' specifications, such as
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* a. length of each type of segment
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* b. frequency of each type of segment.
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* c. routing channel width
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* 2. Estimate the number of nodes in the rr_graph
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* This will estimate the number of
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* a. IPINs, input pins of each grid
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* b. OPINs, output pins of each grid
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* c. SOURCE, virtual node which drives OPINs
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* d. SINK, virtual node which is connected to IPINs
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* e. CHANX and CHANY, routing segments of each channel
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* 3. Create the connectivity of OPINs
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* a. Evenly assign connections to OPINs to routing tracks
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* b. the connection pattern should be same across the fabric
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* 4. Create the connectivity of IPINs
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* a. Evenly assign connections from routing tracks to IPINs
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* b. the connection pattern should be same across the fabric
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* 5. Create the switch block patterns,
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* It is based on the type of switch block, the supported patterns are
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* a. Disjoint, which connects routing track (i)th from (i)th and (i)th routing segments
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* b. Universal, which connects routing track (i)th from (i)th and (M-i)th routing segments
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* c. Wilton, which rotates the connection of Disjoint by 1 track
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* 6. Allocate rr_graph, fill the node information
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* For each node, fill
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* a. basic information: coordinator(xlow, xhigh, ylow, yhigh), ptc_num
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* b. edges (both incoming and outcoming)
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* c. handle direct-connections
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* 7. Build fast look-up for the rr_graph
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* 8. Allocate external data structures
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* a. cost_index
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* b. RC tree
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***********************************************************************/
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t_rr_graph build_tileable_unidir_rr_graph(INP int L_num_types,
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INP t_type_ptr types, INP int L_nx, INP int L_ny,
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INP struct s_grid_tile **L_grid, INP int chan_width,
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INP struct s_chan_width_dist *chan_capacity_inf,
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INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types,
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INP int num_switches, INP t_segment_inf * segment_inf,
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INP int global_route_switch, INP int delayless_switch,
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INP t_timing_inf timing_inf, INP int wire_to_ipin_switch,
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INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs,
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INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings,
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/*Xifan TANG: Switch Segment Pattern Support*/
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INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
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INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) {
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/* Create an empty graph */
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t_rr_graph rr_graph;
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rr_graph.rr_node_indices = NULL;
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rr_graph.rr_node = NULL;
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rr_graph.num_rr_nodes = 0;
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/* Reset warning flag */
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*Warnings = RR_GRAPH_NO_WARN;
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/************************************************************************
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* 1. Assign the segments for each routing channel,
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* To be specific, for each routing track, we assign a routing segment.
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* The assignment is subject to users' specifications, such as
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* a. length of each type of segment
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* b. frequency of each type of segment.
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* c. routing channel width
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***********************************************************************/
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/* Check the channel width */
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int nodes_per_chan = chan_width;
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assert(chan_width > 0);
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t_seg_details *seg_details = NULL;
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seg_details = alloc_and_load_seg_details(&nodes_per_chan,
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std::max(L_nx, L_ny),
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num_seg_types, segment_inf,
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TRUE, FALSE, UNI_DIRECTIONAL);
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/************************************************************************
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* 3. Create the connectivity of OPINs
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* a. Evenly assign connections to OPINs to routing tracks
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* b. the connection pattern should be same across the fabric
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***********************************************************************/
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int **Fc_in = NULL; /* [0..num_types-1][0..num_pins-1] */
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boolean Fc_clipped;
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Fc_clipped = FALSE;
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Fc_in = alloc_and_load_actual_fc(L_num_types, types, nodes_per_chan,
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FALSE, UNI_DIRECTIONAL, &Fc_clipped, ignore_Fc_0);
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if (Fc_clipped) {
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*Warnings |= RR_GRAPH_WARN_FC_CLIPPED;
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}
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/************************************************************************
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* 4. Create the connectivity of IPINs
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* a. Evenly assign connections from routing tracks to IPINs
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* b. the connection pattern should be same across the fabric
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***********************************************************************/
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int **Fc_out = NULL; /* [0..num_types-1][0..num_pins-1] */
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Fc_clipped = FALSE;
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Fc_out = alloc_and_load_actual_fc(L_num_types, types, nodes_per_chan,
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TRUE, UNI_DIRECTIONAL, &Fc_clipped, ignore_Fc_0);
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/************************************************************************
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* 6. Allocate rr_graph, fill the node information
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* For each node, fill
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* a. basic information: coordinator(xlow, xhigh, ylow, yhigh), ptc_num
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* b. edges (both incoming and outcoming)
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* c. handle direct-connections
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***********************************************************************/
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/* Alloc node lookups, count nodes, alloc rr nodes */
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rr_graph.num_rr_nodes = 0;
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rr_graph.rr_node_indices = alloc_and_load_rr_node_indices(nodes_per_chan, L_nx, L_ny,
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&(rr_graph.num_rr_nodes), seg_details);
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rr_graph.rr_node = (t_rr_node *) my_malloc(sizeof(t_rr_node) * rr_graph.num_rr_nodes);
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memset(rr_node, 0, sizeof(t_rr_node) * rr_graph.num_rr_nodes);
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boolean* L_rr_edge_done = (boolean *) my_malloc(sizeof(boolean) * rr_graph.num_rr_nodes);
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memset(L_rr_edge_done, 0, sizeof(boolean) * rr_graph.num_rr_nodes);
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/* handle direct-connections */
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t_clb_to_clb_directs* clb_to_clb_directs = NULL;
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if (num_directs > 0) {
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clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs);
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}
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/************************************************************************
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* 8. Allocate external data structures
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* a. cost_index
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* b. RC tree
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***********************************************************************/
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rr_graph_externals(timing_inf, segment_inf, num_seg_types, nodes_per_chan,
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wire_to_ipin_switch, base_cost_type);
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return rr_graph;
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}
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/************************************************************************
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* End of file : rr_graph_tileable_builder.c
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***********************************************************************/
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@ -0,0 +1,18 @@
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#ifndef RR_GRAPH_TILEABLE_BUILDER_H
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#define RR_GRAPH_TILEABLE_BUILDER_H
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t_rr_graph build_tileable_unidir_rr_graph(INP int L_num_types,
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INP t_type_ptr types, INP int L_nx, INP int L_ny,
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INP struct s_grid_tile **L_grid, INP int chan_width,
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INP struct s_chan_width_dist *chan_capacity_inf,
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INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types,
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INP int num_switches, INP t_segment_inf * segment_inf,
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INP int global_route_switch, INP int delayless_switch,
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INP t_timing_inf timing_inf, INP int wire_to_ipin_switch,
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INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs,
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INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings,
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/*Xifan TANG: Switch Segment Pattern Support*/
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INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns,
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INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges);
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#endif
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