diff --git a/README.md b/README.md index 8429c4d78..903cad90c 100644 --- a/README.md +++ b/README.md @@ -13,17 +13,15 @@ The different ways of compiling can be found in the [**./compilation**](https:// Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md). **Compilation steps:** -1. Clone the repository (git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA) -2. Create a folder named build in OpenPFGA repository (mkdir build && cd build) -3. Create Makefile in this folder using cmake (cmake .. -DCMAKE_BUILD_TYPE=debug) -4. Compile the tool and its dependencies (make) - -*We currently implemented OpenFPGA for:* - -*1. Ubuntu 16.04* -*2. Red Hat 7.5* -*3. MacOS High Sierra 10.13.4* +1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go into it* +2. mkdir build && cd build # *Create a folder named build in OpenPFGA repository* +3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create Makefile in this folder using cmake* +4. make # *Compile the tool and its dependencies* +*We currently implemented OpenFPGA for:*
+*1. Ubuntu 16.04*
+*2. Red Hat 7.5*
+*3. MacOS Mojiva 10.13.4*

*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.* ## Documentation diff --git a/docs/source/fpga_bitstream/command_line_usage.rst b/docs/source/fpga_bitstream/command_line_usage.rst index 839ac7fa9..278bee494 100644 --- a/docs/source/fpga_bitstream/command_line_usage.rst +++ b/docs/source/fpga_bitstream/command_line_usage.rst @@ -1,4 +1,14 @@ Command-line Options for FPGA Bitstream Generator ================================================= -**Under Construction** \ No newline at end of file +All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find: + +FPGA-Verilog Supported Option:: + + --fpga_bitstream_generator + +.. csv-table:: Commmand-line Option of FPGA-Bitstream + :header: "Command Options", "Description" + :widths: 15, 30 + + "--fpga_bitstream_generator", "Turn on the FPGA-Bitstream and output a .bitstream file containing FPGA configuration." diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst index dfe34eaea..656b2ecef 100644 --- a/docs/source/fpga_verilog/command_line_usage.rst +++ b/docs/source/fpga_verilog/command_line_usage.rst @@ -21,7 +21,6 @@ FPGA-Verilog Supported Options:: :widths: 15, 30 "--fpga_verilog", "Turn on the FPGA-Verilog." -<<<<<<< HEAD "--fpga_verilog_dir ", "Specify the directory that all the Verilog files will be outputted to is the destination directory." "--fpga_verilog_include_timing", "Includes the timings found in the XML file." "--fpga_verilog_init_sim", "Initializes the simulation for ModelSim." @@ -30,7 +29,6 @@ FPGA-Verilog Supported Options:: "--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck." "--fpga_verilog_print_top_auto_testbench \ ", "Prints the testbench associated with the given benchmark. Determines the type of autodeck." -======= "--fpga_verilog_dir ", "Specify the directory where all the Verilog files will be outputted to. is the destination directory." "--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file." "--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case" @@ -46,8 +44,6 @@ FPGA-Verilog Supported Options:: "--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR" "--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool" "--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping" - "", "" ->>>>>>> f56adc681567b73c7826228641e089482dffc009 .. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: diff --git a/tutorials/fpga_flow/folder_organization.md b/tutorials/fpga_flow/folder_organization.md index 095325ad7..172f10782 100644 --- a/tutorials/fpga_flow/folder_organization.md +++ b/tutorials/fpga_flow/folder_organization.md @@ -17,10 +17,10 @@ In this folder are saved the architecture files. These files are Hardware descri This folder contains benchmarks to implement in the FPGA. it's divided in 3 folders: - **Blif**: Contains .blif and .act file to use in OpenFPGA. Benchmarks are divided in folder with the same name as the top module - **Verilog**: Contains Verilog netlist of benchmarks to use in OpenFPGA. Each project is saved in a folder with the same name as the top module. -- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#benchmark-list) +- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#benchmark-list) ## configs -This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#configuration-file) +This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#configuration-file) ## scripts This folder contains scripts call by OpenFPGA flow. Some of them can be used out of the flow as **pro_blif.pl** and **rewrite_path_in_file.pl** which respectively rewrite a blif file with 3 members on a ".latch" module to let it have 5 and replace a keyword in a file.
diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md index 27c9b1db6..656953b3e 100644 --- a/tutorials/fpga_flow/how2use.md +++ b/tutorials/fpga_flow/how2use.md @@ -1,7 +1,7 @@ # FPGA flow This tutorial will help the user to understand how to use OpenFPGA flow.
-During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/folder_organization.md). +During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md). ## Running fpga_flow.pl @@ -16,7 +16,7 @@ cd fpga_flow
By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
-The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md).
+The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).
There is 3 important things to see: - All FPGA-Verilog options have been activated - fpga_flow.pl calls a configuration file through "config_file" variable diff --git a/tutorials/tutorial_index.md b/tutorials/tutorial_index.md index c6013d6dc..8198fb6da 100644 --- a/tutorials/tutorial_index.md +++ b/tutorials/tutorial_index.md @@ -3,8 +3,8 @@ OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.

These tutorials are organized as follow: -* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md) -* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md) +* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md) +* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md) * Architecture modification ## Folder organization diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index a0d765a89..78b956ce3 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -102,7 +102,7 @@ struct s_TokenPair OptionBaseTokenList[] = { { "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */ /* Xifan Tang: Bitstream generator */ { "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */ - { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ + // { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated /* mrFPGA: Xifan TANG */ {"show_sram", OT_SHOW_SRAM}, {"show_pass_trans", OT_SHOW_PASS_TRANS}, diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index b90b90f4f..108e9d355 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -562,8 +562,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { /* Xifan TANG: Bitstream generator */ case OT_FPGA_BITSTREAM_GENERATOR: return Args; - case OT_FPGA_BITSTREAM_OUTPUT_FILE: - return ReadString(Args, &Options->fpga_bitstream_file); +// case OT_FPGA_BITSTREAM_OUTPUT_FILE: // AA: temporarily deprecated +// return ReadString(Args, &Options->fpga_bitstream_file); /* mrFPGA: Xifan TANG */ case OT_SHOW_SRAM: case OT_SHOW_PASS_TRANS: diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 023b2df92..7d1730883 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -213,8 +213,8 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n"); /* Xifan Tang: Bitstream generator */ vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file \n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n"); +// vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file \n"); // AA: temporarily deprecated } void vpr_init_file_handler() { diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index c93eb7d49..8007363cf 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path