From 1cf066d3add16f80da18510d690d558c34fcc863 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Thu, 6 Sep 2018 14:25:23 -0600 Subject: [PATCH] Fixing minor bugs --- ace2/Makefile | 2 +- .../fpga_spice/k6_N10_sram_tsmc40nm_TT.conf | 16 ++++---- fpga_flow/run_fpga_spice_testbench_study.sh | 8 +--- fpga_flow/scripts/fpga_flow.pl | 10 ++++- .../base/fpga_spice_backannotate_utils.c | 4 +- .../SRC/fpga_spice/base/fpga_spice_utils.c | 40 ++++++++++++++++--- 6 files changed, 56 insertions(+), 24 deletions(-) diff --git a/ace2/Makefile b/ace2/Makefile index 2d868865a..ccd6b4f29 100644 --- a/ace2/Makefile +++ b/ace2/Makefile @@ -4,7 +4,7 @@ LFLAGS = -g -O0 EXE = ace -ABC_DIR = ../../../../research/vtr_release/abc_with_bb_support +ABC_DIR = ../abc_with_bb_support ABC_LIB = libabc.a ABC_LIB_PATH = $(ABC_DIR)/$(ABC_LIB) diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf index fe41deb8d..727c6120d 100644 --- a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf +++ b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf @@ -1,26 +1,26 @@ # Standard Configuration Example [dir_path] -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 -benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench +script_base = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/scripts/ +#benchmark_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/benchmarks/MCNC_big20 +benchmark_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench odin2_path = /research/ece/lnis/USERS/tang/research/EDA/vtr7_release/ODIN_II/odin_II.exe cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc -abc_path = /research/ece/lnis/USERS/tang/research/EDA/ABC/abc20160717/abc +abc_path = /research/ece/lnis/USERS/tang/research/EDA/ABC/abc70930/abc abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc -abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/EDA/vtr_release/abc_with_bb_support/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/abc_with_bb_support/abc mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 -#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr vpr_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_rram/vpr/vpr rpt_dir = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/results -ace_path = /research/ece/lnis/USERS/tang/research/EDA/vtr_release/ace2/ace +ace_path = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/ace2/ace [flow_conf] flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr #flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr vpr_arch = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +m2net_conf = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf mpack2_arch = K6_pattern7_I24.arch power_tech_xml = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/tech/tsmc40nm.xml # Use relative path under VPR folder is OK @@ -28,4 +28,4 @@ power_tech_xml = /research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/fpga_flow/t mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: mpack2_tags = BLE Number:|BLE Fill Rate: vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing +vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff diff --git a/fpga_flow/run_fpga_spice_testbench_study.sh b/fpga_flow/run_fpga_spice_testbench_study.sh index 610c76656..0b4b60492 100644 --- a/fpga_flow/run_fpga_spice_testbench_study.sh +++ b/fpga_flow/run_fpga_spice_testbench_study.sh @@ -6,18 +6,14 @@ set corner_list = (TT) foreach j ($corner_list) #rm -rf ./results - cd ./scripts - if ($j == MC) then set mc_opt = (-monte_carlo detail_rpt) else set mc_opt = () endif - perl fpga_flow.pl -conf ../configs/fpga_spice/k6_N10_sram_tsmc40nm_$j\.conf -benchmark ../benchmarks/fpga_spice_bench.txt -rpt ../csv_rpts/fpga_spice/k6_N10_sram_tsmc40nm_bench_$j\.csv -N 10 -K 6 -power -remove_designs -multi_thread 1 -vpr_fpga_spice ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm -vpr_fpga_spice_rename_illegal_port -vpr_fpga_spice_sim_mt_num 16 -vpr_fpga_spice_print_top_tb -vpr_fpga_spice_print_component_tb -vpr_fpga_spice_print_grid_tb #-vpr_fpga_spice_parasitic_net_estimation_off #-vpr_fpga_spice_leakage_only + perl scripts/fpga_flow.pl -conf ./configs/fpga_spice/k6_N10_sram_tsmc40nm_$j\.conf -benchmark ./benchmarks/fpga_spice_bench.txt -rpt ./csv_rpts/fpga_spice/k6_N10_sram_tsmc40nm_bench_$j\.csv -N 10 -K 6 -power -remove_designs -multi_thread 1 -vpr_fpga_spice ./vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm -vpr_fpga_spice_rename_illegal_port -vpr_fpga_spice_sim_mt_num 16 -vpr_fpga_spice_print_top_tb -vpr_fpga_spice_print_component_tb -vpr_fpga_spice_print_grid_tb #-vpr_fpga_spice_parasitic_net_estimation_off #-vpr_fpga_spice_leakage_only - perl run_fpga_spice.pl -conf ../vpr_fpga_spice_conf/sample.conf -task ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm_standard.txt -rpt ../vpr_fpga_spice_csv_rpts/k6_N10_sram_tsmc40_spice_bench_$j\.csv $mc_opt -parse_top_tb -multi_thread 2 -parse_pb_mux_tb -parse_cb_mux_tb -parse_sb_mux_tb -parse_lut_tb -parse_hardlogic_tb -parse_grid_tb -parse_cb_tb -parse_sb_tb - - cd .. + perl scripts/run_fpga_spice.pl -conf ./vpr_fpga_spice_conf/sample.conf -task ./vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm_standard.txt -rpt ./vpr_fpga_spice_csv_rpts/k6_N10_sram_tsmc40_spice_bench_$j\.csv $mc_opt -parse_top_tb -multi_thread 2 -parse_pb_mux_tb -parse_cb_mux_tb -parse_sb_mux_tb -parse_lut_tb -parse_hardlogic_tb -parse_grid_tb -parse_cb_tb -parse_sb_tb end diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 6bc9b137b..087d94572 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -58,7 +58,8 @@ my @sctgy; "csv_tags", ); # refer to the keywords of dir_path -@{$sctgy[0]} = ("benchmark_dir", +@{$sctgy[0]} = ("script_base", + "benchmark_dir", "odin2_path", "cirkit_path", "abc_mccl_path", @@ -1034,7 +1035,12 @@ sub run_odin2($ $ $) { sub run_pro_blif($ $) { my ($abc_blif_out_bak, $abc_blif_out) = @_; - `perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; + my ($pro_blif_path) = ($conf_ptr->{dir_path}->{script_base}->{val}); + + $pro_blif_path =~ s/\/$//g; + $pro_blif_path = $pro_blif_path . "/pro_blif.pl"; + + `perl $pro_blif_path -i $abc_blif_out_bak -o $abc_blif_out`; if (!(-e $abc_blif_out)) { die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; diff --git a/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_backannotate_utils.c b/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_backannotate_utils.c index 3d8c99fea..32245b963 100644 --- a/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_backannotate_utils.c +++ b/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_backannotate_utils.c @@ -639,7 +639,7 @@ void backannotate_clb_nets_act_info() { for (inet = 0; inet < num_logical_nets; inet++) { if (NULL == vpack_net[inet].spice_net_info) { /* Allocate */ - vpack_net[inet].spice_net_info = (t_spice_net_info*)my_malloc(sizeof(t_spice_net_info)); + vpack_net[inet].spice_net_info = (t_spice_net_info*)my_calloc(1, sizeof(t_spice_net_info)); } /* Initialize to zero */ init_spice_net_info(vpack_net[inet].spice_net_info); @@ -660,7 +660,7 @@ void backannotate_clb_nets_act_info() { for (inet = 0; inet < num_nets; inet++) { if (NULL == clb_net[inet].spice_net_info) { /* Allocate */ - clb_net[inet].spice_net_info = (t_spice_net_info*)my_malloc(sizeof(t_spice_net_info)); + clb_net[inet].spice_net_info = (t_spice_net_info*)my_calloc(1, sizeof(t_spice_net_info)); } /* Initialize to zero */ init_spice_net_info(clb_net[inet].spice_net_info); diff --git a/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_utils.c b/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_utils.c index 264f56c61..605deb44b 100644 --- a/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_utils.c +++ b/vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_utils.c @@ -5647,6 +5647,38 @@ void configure_lut_sram_bits_per_line_rec(int** sram_bits, return; } +/* Determine if the truth table of a LUT is a on-set or a off-set */ +int determine_lut_truth_table_on_set(int truth_table_len, + char** truth_table) { + int on_set = 0; + int off_set = 0; + int i, tt_line_len; + + for (i = 0; i < truth_table_len; i++) { + tt_line_len = strlen(truth_table[i]); + switch (truth_table[i][tt_line_len - 1]) { + case '1': + on_set = 1; + break; + case '0': + off_set = 1; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid truth_table_line ending(=%c)!\n", + __FILE__, __LINE__, truth_table[i][tt_line_len - 1]); + exit(1); + } + } + + /* Prefer on_set if both are true */ + if (1 == (on_set + off_set)) { + on_set = 1; off_set = 0; + } + + return on_set; +} + + int* generate_lut_sram_bits(int truth_table_len, char** truth_table, int lut_size, @@ -5674,6 +5706,9 @@ int* generate_lut_sram_bits(int truth_table_len, __FILE__, __LINE__, default_sram_bit_value); exit(1); } + } else { + on_set = determine_lut_truth_table_on_set(truth_table_len, truth_table); + off_set = 1 - on_set; } /* Read in truth table lines, decode one by one */ @@ -5682,11 +5717,6 @@ int* generate_lut_sram_bits(int truth_table_len, //printf("truth_table[%d] = %s\n", i, truth_table[i]); completed_truth_table[i] = complete_truth_table_line(lut_size, truth_table[i]); //printf("Completed_truth_table[%d] = %s\n", i, completed_truth_table[i]); - if (0 == strcmp(" 1", completed_truth_table[i] + lut_size)) { - on_set = 1; - } else if (0 == strcmp(" 0", completed_truth_table[i] + lut_size)) { - off_set = 1; - } } //printf("on_set=%d off_set=%d", on_set, off_set); assert(1 == (on_set + off_set));