From 817729ac868312019294393bf2b55d5853d00ecf Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Mon, 1 Mar 2021 22:31:15 -0800 Subject: [PATCH 1/6] Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables --- openfpga_flow/misc/qlf_yosys.ys | 2 +- openfpga_flow/scripts/run_fpga_flow.py | 16 ++++++++++++++++ openfpga_flow/scripts/run_fpga_task.py | 12 ++++++++++++ .../flow_test/config/task.conf | 19 +++---------------- 4 files changed, 32 insertions(+), 17 deletions(-) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index 131bddd3c..4b861a8c9 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -2,5 +2,5 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE} +synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE} diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 66472e3c8..3927459e9 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -99,6 +99,10 @@ parser.add_argument('--arch_variable_file', type=str, default=None, # help="Key file for shell") parser.add_argument('--yosys_tmpl', type=str, default=None, help="Alternate yosys template, generates top_module.blif") +parser.add_argument('--yosys_mode', type=str, default=None, + help="Specify adder/no_adder mode for yosys run. Default is adder") +parser.add_argument('--yosys_family', type=str, default="qlf_k4n8", + help="Specify device family for yosys run") parser.add_argument('--disp', action="store_true", help="Open display while running VPR") parser.add_argument('--debug', action="store_true", @@ -480,6 +484,16 @@ def run_yosys_with_abc(): logger.exception("Failed to extract lut_size from XML file") clean_up_and_exit("") args.K = lut_size + + YS_MODE="" + # Yosys valid mode option is "no_adder". + if args.yosys_mode is not None: + if args.yosys_mode.lower() == "no_adder": + YS_MODE = "-" + args.yosys_mode + else: + logger.warning("Invalid value '" + args.yosys_mode + "' specified for synthesis_param 'bench_yosys_mode'") + logger.warning("Considering default yosys mode i.e. adder mode") + # Yosys script parameter mapping ys_params = { "READ_VERILOG_FILE": " \n".join([ @@ -488,6 +502,8 @@ def run_yosys_with_abc(): "TOP_MODULE": args.top_module, "LUT_SIZE": lut_size, "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", + "YOSYS_FAMILY": args.yosys_family, + "YOSYS_MODE": YS_MODE, } yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index fa297932e..2d676c786 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -255,6 +255,8 @@ def generate_each_task_actions(taskname): # Read provided benchmark configurations # Common configurations ys_for_task_common = SynthSection.get("bench_yosys_common") + ys_yosys_mode = SynthSection.get("bench_yosys_mode") + ys_yosys_family = SynthSection.get("bench_yosys_family") chan_width_common = SynthSection.get("bench_chan_width_common") # Individual benchmark configuration @@ -263,6 +265,10 @@ def generate_each_task_actions(taskname): fallback="top") CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys", fallback=ys_for_task_common) + CurrBenchPara["yosys_mode"] = SynthSection.get(bech_name+"_yosys_mode", + fallback=ys_yosys_mode) + CurrBenchPara["yosys_family"] = SynthSection.get(bech_name+"_yosys_family", + fallback=ys_yosys_family) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) @@ -381,6 +387,12 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): if benchmark_obj.get("ys_script"): command += ["--yosys_tmpl", benchmark_obj["ys_script"]] + if benchmark_obj.get("yosys_mode"): + command += ["--yosys_mode", benchmark_obj["yosys_mode"]] + + if benchmark_obj.get("yosys_family"): + command += ["--yosys_family", benchmark_obj["yosys_family"]] + if task_gc.getboolean("power_analysis"): command += ["--power"] command += ["--power_tech", task_gc.get("power_tech_file")] diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 71529c23b..9724609d8 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -48,40 +48,27 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys +bench_yosys_mode=no_adder +bench_yosys_family=qlf_k4n8 bench0_top = io_tc1 -bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench1_top = unsigned_mult_80 -bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench2_top = bin2bcd -bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench3_top = counter -bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench5_top = rs_decoder_top -bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench6_top = top_module -bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench7_top = sha256 -bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench8_top = cavlc_top -bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench9_top = cf_fft_256_8 -bench9_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench10_top = counter120bitx5 #bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench11_top = top -bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench12_top = dct_mac -bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench13_top = des_perf -bench13_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench14_top = diffeq_f_systemC -bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench15_top = i2c_master_top -bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench16_top = iir -bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench17_top = jpeg_qnr -bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench18_top = multi_enc_decx2x4 # sdc_controller requires 4 clocks #bench19_top = sdc_controller From 0cbad747a1628cf8c1dee2c48461007d9963cc91 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Thu, 4 Mar 2021 00:45:19 -0800 Subject: [PATCH 2/6] Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family --- openfpga_flow/scripts/run_fpga_flow.py | 31 +++++++++---------- openfpga_flow/scripts/run_fpga_task.py | 12 ------- .../counter_5clock_test/config/task.conf | 1 + .../flow_test/config/task.conf | 4 +-- 4 files changed, 18 insertions(+), 30 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 3927459e9..bddda8d15 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -99,10 +99,6 @@ parser.add_argument('--arch_variable_file', type=str, default=None, # help="Key file for shell") parser.add_argument('--yosys_tmpl', type=str, default=None, help="Alternate yosys template, generates top_module.blif") -parser.add_argument('--yosys_mode', type=str, default=None, - help="Specify adder/no_adder mode for yosys run. Default is adder") -parser.add_argument('--yosys_family', type=str, default="qlf_k4n8", - help="Specify device family for yosys run") parser.add_argument('--disp', action="store_true", help="Open display while running VPR") parser.add_argument('--debug', action="store_true", @@ -484,16 +480,6 @@ def run_yosys_with_abc(): logger.exception("Failed to extract lut_size from XML file") clean_up_and_exit("") args.K = lut_size - - YS_MODE="" - # Yosys valid mode option is "no_adder". - if args.yosys_mode is not None: - if args.yosys_mode.lower() == "no_adder": - YS_MODE = "-" + args.yosys_mode - else: - logger.warning("Invalid value '" + args.yosys_mode + "' specified for synthesis_param 'bench_yosys_mode'") - logger.warning("Considering default yosys mode i.e. adder mode") - # Yosys script parameter mapping ys_params = { "READ_VERILOG_FILE": " \n".join([ @@ -502,9 +488,22 @@ def run_yosys_with_abc(): "TOP_MODULE": args.top_module, "LUT_SIZE": lut_size, "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", - "YOSYS_FAMILY": args.yosys_family, - "YOSYS_MODE": YS_MODE, } + + for indx in range(0, len(OpenFPGAArgs), 2): + tmpVar = OpenFPGAArgs[indx][2:].upper() + ys_params[tmpVar] = OpenFPGAArgs[indx+1] + + if 'YOSYS_FAMILY' not in ys_params.keys(): + # define default family as 'qlf_k4n8' + ys_params['YOSYS_FAMILY'] = "qlf_k4n8" + + # prefix value of YOSYS_MODE with '-' as an option in yosys script + if 'YOSYS_MODE' in ys_params.keys(): + ys_params['YOSYS_MODE'] = "-" + ys_params['YOSYS_MODE'] + else: + ys_params['YOSYS_MODE'] = "" + yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") tmpl = Template(open(yosys_template, encoding='utf-8').read()) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 2d676c786..fa297932e 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -255,8 +255,6 @@ def generate_each_task_actions(taskname): # Read provided benchmark configurations # Common configurations ys_for_task_common = SynthSection.get("bench_yosys_common") - ys_yosys_mode = SynthSection.get("bench_yosys_mode") - ys_yosys_family = SynthSection.get("bench_yosys_family") chan_width_common = SynthSection.get("bench_chan_width_common") # Individual benchmark configuration @@ -265,10 +263,6 @@ def generate_each_task_actions(taskname): fallback="top") CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys", fallback=ys_for_task_common) - CurrBenchPara["yosys_mode"] = SynthSection.get(bech_name+"_yosys_mode", - fallback=ys_yosys_mode) - CurrBenchPara["yosys_family"] = SynthSection.get(bech_name+"_yosys_family", - fallback=ys_yosys_family) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) @@ -387,12 +381,6 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): if benchmark_obj.get("ys_script"): command += ["--yosys_tmpl", benchmark_obj["ys_script"]] - if benchmark_obj.get("yosys_mode"): - command += ["--yosys_mode", benchmark_obj["yosys_mode"]] - - if benchmark_obj.get("yosys_family"): - command += ["--yosys_family", benchmark_obj["yosys_family"]] - if task_gc.getboolean("power_analysis"): command += ["--power"] command += ["--power_tech", task_gc.get("power_tech_file")] diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf index df236e1cf..3b68a8b83 100644 --- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf @@ -21,6 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml +yosys_mode = no_adder [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 9724609d8..eba623ee8 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_circuit_format=eblif +yosys_mode = no_adder [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -49,8 +50,7 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys -bench_yosys_mode=no_adder -bench_yosys_family=qlf_k4n8 + bench0_top = io_tc1 bench1_top = unsigned_mult_80 bench2_top = bin2bcd From 2b2acae75795c850675496d069eda5cebc6bc706 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Fri, 5 Mar 2021 04:05:19 -0800 Subject: [PATCH 3/6] Adding command to generate verilog file out of yosys run --- openfpga_flow/misc/qlf_yosys.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index 4b861a8c9..638103885 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -4,3 +4,4 @@ ${READ_VERILOG_FILE} synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE} +write_verilog -noattr -nohex ${TOP_MODULE}.v \ No newline at end of file From ce76c58422cd64ab4f89903e2f4a97df3a727764 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Fri, 5 Mar 2021 09:06:05 -0800 Subject: [PATCH 4/6] add shift register test case --- .../shift_reg_8192/rtl/shift_reg_8192.v | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v diff --git a/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v b/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v new file mode 100644 index 000000000..bd86b9bcc --- /dev/null +++ b/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v @@ -0,0 +1,24 @@ +//-----------------------------------------------------// +// Design Name : Shift_reg +// File Name : Shift_reg_8192.v +// Function : Shift register +//------------------------------------------------------// + + +module shift_reg_8192 #( parameter size = 8191 ) (shift_in, clk, shift_out); + + // Port Declaration + input shift_in; + input clk; + output shift_out; + + reg [ size:0 ] shift; // shift register + + always @ (posedge clk) + begin + shift = { shift[size-1:0] , shift_in } ; + end + + assign shift_out = shift[size]; + +endmodule From 6a1ce0108443000fcaafbdbdb7648dd8c4941330 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 7 Mar 2021 22:01:35 -0800 Subject: [PATCH 5/6] Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS --- openfpga_flow/misc/qlf_yosys.ys | 2 +- openfpga_flow/scripts/run_fpga_flow.py | 10 ---------- .../tasks/quicklogic_tests/flow_test/config/task.conf | 2 +- 3 files changed, 2 insertions(+), 12 deletions(-) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index 638103885..c90b8c5ac 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -2,6 +2,6 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE} +synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS} write_verilog -noattr -nohex ${TOP_MODULE}.v \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index bddda8d15..e91d34a78 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -494,16 +494,6 @@ def run_yosys_with_abc(): tmpVar = OpenFPGAArgs[indx][2:].upper() ys_params[tmpVar] = OpenFPGAArgs[indx+1] - if 'YOSYS_FAMILY' not in ys_params.keys(): - # define default family as 'qlf_k4n8' - ys_params['YOSYS_FAMILY'] = "qlf_k4n8" - - # prefix value of YOSYS_MODE with '-' as an option in yosys script - if 'YOSYS_MODE' in ys_params.keys(): - ys_params['YOSYS_MODE'] = "-" + ys_params['YOSYS_MODE'] - else: - ys_params['YOSYS_MODE'] = "" - yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") tmpl = Template(open(yosys_template, encoding='utf-8').read()) diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index eba623ee8..824d92301 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_circuit_format=eblif -yosys_mode = no_adder +yosys_args = -no_adder -family qlf_k4n8 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml From 7945628307682a2a9a113953c61483f68d9bad39 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 7 Mar 2021 22:25:01 -0800 Subject: [PATCH 6/6] Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification --- .../quicklogic_tests/counter_5clock_test/config/task.conf | 2 +- .../tasks/quicklogic_tests/lut_adder_test/config/task.conf | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf index 3b68a8b83..92c91491e 100644 --- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml -yosys_mode = no_adder +yosys_args = -no_adder -family qlf_k4n8 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 6a5f29063..6f711649b 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -21,6 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml openfpga_vpr_circuit_format=eblif +yosys_args = -family qlf_k4n8 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -37,5 +38,5 @@ bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys # The output verilog of yosys is not synthesizable!!! # Turn off verification for now # SHOULD focus on fixing the Verilog problem and run verification at the end of the flow -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist=