From 1c4dc9f74b75374a75afb86221a81950392b8791 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Feb 2021 11:49:59 -0700 Subject: [PATCH] [Doc] Update documentation about the super LUT feature --- .../arch_lang/circuit_model_examples.rst | 65 ++++++- .../arch_lang/figures/lut_arith_example.svg | 177 ++++++++++++++++++ docs/source/overview/tech_highlights.rst | 106 ++++++----- 3 files changed, 293 insertions(+), 55 deletions(-) create mode 100644 docs/source/manual/arch_lang/figures/lut_arith_example.svg diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index 263ee1724..a7a6dba97 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -689,8 +689,8 @@ Template - - + + @@ -736,18 +736,22 @@ Template .. note:: For a LUT, three types of ports (``input``, ``output`` and ``sram``) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. -.. option:: +.. option:: - ``tri_state_map="[-|1]"`` Customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, ``tri_state_map="----11"`` indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. - ``circuit_model_name=""`` Specify the circuit model to build logic gates in order to tri-state the inputs in fracturable LUT modes. It is required to use an ``AND`` gate to force logic '0' or an ``OR`` gate to force logic '1' for the input ports. -.. option:: + - ``is_harden_lut_port="[true|false]"`` Specify if the input drives a harden logic inside a LUT. A harden input is supposed **NOT** to drive any multiplexer input (the internal multiplexer of LUT). As a result, such inputs are not considered to implement any truth table mapped to the LUT. If enabled, the input will **NOT** be considered for wiring to internal multiplexers as well as bitstream generation. By default, an input port is treated **NOT** to be a harden LUT port. + +.. option:: - ``lut_frac_level=""`` Specify the level in LUT multiplexer tree where the output port are wired to. For example, ``lut_frac_level="4"`` in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. - ``lut_output_mask=""`` Describe which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. ``lut_output_mask="0,2"`` indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. + - ``is_harden_lut_port="[true|false]"`` Specify if the output is driven by a harden logic inside a LUT. A harden input is supposed **NOT** to be driven by any multiplexer output (the internal multiplexer of LUT). As a result, such outputs are not considered to implement any truth table mapped to the LUT. If enabled, the output will **NOT** be considered for wiring to internal multiplexers as well as bitstream generation. By default, an output port is treated **NOT** to be a harden LUT port. + .. note:: The size of the output port should be consistent to the length of ``lut_output_mask``. .. option:: @@ -912,6 +916,54 @@ This example shows: - There will be two outputs wired to the 5th stage of routing multiplexer (the outputs of dual 5-input LUTs) +.. _circuit_model_lut_harden_logic_example: + +LUT with Harden Logic +````````````````````` +:numref:`fig_lut_arith` illustrates the detailed schematic of a fracturable 4-input LUT coupled with carry logic gates. For fracturable LUT schematic, please refer to :numref:`fig_std_frac_lut`. +This feature allows users to fully customize their LUT circuit implementation while being compatible with OpenFPGA's bitstream generator when mapping truth tables to the LUTs. + +.. warning:: OpenFPGA does **NOT** support netlist autogeneration for the LUT with harden logic. Users should build their own netlist and use ``verilog_netlist`` syntax of :ref:`circuit_library` to include it. + +.. _fig_lut_arith: + +.. figure:: ./figures/lut_arith_example.svg + :scale: 80% + :alt: detailed lut composition + + Detailed schematic of a fracturable 4-input LUT with embedded carry logic. + +The code describing this LUT is: + +.. code-block:: xml + + + + + + + + + + + + + + + + + + +This example shows: + - Fracturable 4-input LUT which is configurable by 16 SRAM cells. + - There are two output wired to the 3th stage of routing multiplexer (the outputs of dual 3-input LUTs) + - There are two outputs wired to the 2th stage of routing multiplexer (the outputs of 2-input LUTs in the in the lower part of SRAM cells). Note that the two outputs drive the embedded carry logic + - There is a harden carry logic, i.e., a 2-input MUX, to implement high-performance carry function. + - There is a mode-switch multiplexer at ``cin`` port, which is used to switch between arithemetic mode and regular LUT mode. + +.. note:: If the embedded harden logic are driven partially by LUT outputs, users may use the :ref:`file_formats_bitstream_setting` to gaurantee correct bitstream generation for the LUTs. + + Flip-Flops ~~~~~~~~~~ @@ -1012,6 +1064,8 @@ This example shows: - The first output port **MUST** be the data output port, e.g., ``Q``. - The second output port **MUST** be the **inverted** data output port, e.g., ``QN``. +.. _circuit_model_ccff_enable_example: + Configuration-chain Flip-flop with Configure Enable Signals ``````````````````````````````````````````````````````````` @@ -1049,6 +1103,9 @@ The code describing this FF is: - The second output port **MUST** be the **inverted** data output port which is activated by the configure enable signal, e.g., ``QN``. - The second output port **MUST** be the data output port which is activated by the configure enable signal, e.g., ``Q``. + +.. _circuit_model_ccff_scanable_example: + Configuration-chain Flip-flop with Scan Input ````````````````````````````````````````````` diff --git a/docs/source/manual/arch_lang/figures/lut_arith_example.svg b/docs/source/manual/arch_lang/figures/lut_arith_example.svg new file mode 100644 index 000000000..42107e8d0 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/lut_arith_example.svg @@ -0,0 +1,177 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.2\n2021-02-10 18:07:14 +0000 + + arith_lut + + 图层 1 + + + + + + + + + + + + Fractu + rable + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + cin + + + + + + + + + M + U + X + + + + + LUT2_out[1] + + + + + + + + + + + + MUX + + + + + LUT2_out[0] + + + + + + + + + + + + + + + cout + + + + + + + + + + + mode[0] + + + + + + + + mode[1] + + + + + diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index fa1a364e3..95521cc29 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -1,61 +1,65 @@ Technical Highlights -------------------- -The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of October 2020**) +The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of February 2021**) Supported Circuit Designs ~~~~~~~~~~~~~~~~~~~~~~~~~ -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Circuit Types | Auto-generation | User-Defined | Design Topologies | -+===============+=================+==============+=====================================================+ -| Inverter | Yes | Yes | - :ref:`circuit_model_power_gated_inverter_example` | -| | | | - :ref:`circuit_model_inverter_1x_example` | -| | | | - :ref:`circuit_model_tapered_inv_16x_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Buffer | Yes | Yes | - :ref:`circuit_model_buffer_2x_example` | -| | | | - :ref:`circuit_model_power_gated_buffer_example` | -| | | | - :ref:`circuit_model_tapered_buffer_64x_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| AND gate | Yes | Yes | - :ref:`circuit_model_and2_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| OR gate | Yes | Yes | - :ref:`circuit_model_or2_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| MUX2 gate | Yes | Yes | - :ref:`circuit_model_mux2_gate_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Pass gate | Yes | Yes | - :ref:`circuit_model_tgate_example` | -| | | | - :ref:`circuit_model_pass_transistor_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Look-Up Table | Yes | Yes | - **Any size** | -| | | | - :ref:`circuit_model_single_output_lut_example` | -| | | | - :ref:`circuit_model_frac_lut_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Routing | Yes | No | - **Any size** | -| Multiplexer | | | - :ref:`circuit_model_mux_multilevel_example` | -| | | | - :ref:`circuit_model_mux_1level_example` | -| | | | - :ref:`circuit_model_mux_tree_example` | -| | | | - :ref:`circuit_model_mux_stdcell_example` | -| | | | - :ref:`circuit_model_mux_local_encoder_example` | -| | | | - :ref:`circuit_model_mux_const_input_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` | -| Memory | | | - :ref:`circuit_model_sram_blwl_example` | -| | | | - :ref:`circuit_model_dff_example` | -| | | | - :ref:`circuit_model_ccff_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Block RAM | No | Yes | - **Any size** | -| | | | - Single-port | -| | | | - Dual-port | -| | | | - Fracturable | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| Arithmetic | No | Yes | - **Any size** | -| Units | | | - Multiplier | -| | | | - :ref:`circuit_model_full_adder_example` | -+---------------+-----------------+--------------+-----------------------------------------------------+ -| I/O | No | Yes | - :ref:`circuit_model_gpio_example` | -| | | | - Bi-directional buffer | -| | | | - AIB | -+---------------+-----------------+--------------+-----------------------------------------------------+ ++-----------------+--------------+-----------+-----------------------------------------------------+ +| | Circuit Types | | Auto- | | User- | | Design Topologies | +| | | | generation | | Defined | | ++=================+==============+===========+=====================================================+ +| Inverter | Yes | Yes | - :ref:`circuit_model_power_gated_inverter_example` | +| | | | - :ref:`circuit_model_inverter_1x_example` | +| | | | - :ref:`circuit_model_tapered_inv_16x_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| Buffer | Yes | Yes | - :ref:`circuit_model_buffer_2x_example` | +| | | | - :ref:`circuit_model_power_gated_buffer_example` | +| | | | - :ref:`circuit_model_tapered_buffer_64x_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| AND gate | Yes | Yes | - :ref:`circuit_model_and2_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| OR gate | Yes | Yes | - :ref:`circuit_model_or2_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| MUX2 gate | Yes | Yes | - :ref:`circuit_model_mux2_gate_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| Pass gate | Yes | Yes | - :ref:`circuit_model_tgate_example` | +| | | | - :ref:`circuit_model_pass_transistor_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| Look-Up Table | Yes | Yes | - **Any size** | +| | | | - :ref:`circuit_model_single_output_lut_example` | +| | | | - :ref:`circuit_model_frac_lut_example` | +| | | | - :ref:`circuit_model_lut_harden_logic_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| | Routing | Yes | No | - **Any size** | +| | Multiplexer | | | - :ref:`circuit_model_mux_multilevel_example` | +| | | | - :ref:`circuit_model_mux_1level_example` | +| | | | - :ref:`circuit_model_mux_tree_example` | +| | | | - :ref:`circuit_model_mux_stdcell_example` | +| | | | - :ref:`circuit_model_mux_local_encoder_example` | +| | | | - :ref:`circuit_model_mux_const_input_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| | Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` | +| | Memory | | | - :ref:`circuit_model_sram_blwl_example` | +| | | | - :ref:`circuit_model_dff_example` | +| | | | - :ref:`circuit_model_ccff_example` | +| | | | - :ref:`circuit_model_ccff_enable_example` | +| | | | - :ref:`circuit_model_ccff_scanable_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| Block RAM | No | Yes | - **Any size** | +| | | | - Single-port | +| | | | - Dual-port | +| | | | - Fracturable | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| | Arithmetic | No | Yes | - **Any size** | +| | Units | | | - Multiplier | +| | | | - :ref:`circuit_model_full_adder_example` | ++-----------------+--------------+-----------+-----------------------------------------------------+ +| I/O | No | Yes | - :ref:`circuit_model_gpio_example` | +| | | | - Bi-directional buffer | +| | | | - AIB | ++-----------------+--------------+-----------+-----------------------------------------------------+ * The user defined netlist could come from a standard cell