diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
index 0ae9e46c8..edd21c94c 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
@@ -16,6 +16,9 @@ clean
 # LUT mapping
 abc -lut ${LUT_SIZE}
 
+# FF mapping
+techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG}
+
 # Check
 synth -run check