From 1c2192a87d60b0d1d6682cde68466fae78a9f8a1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Sep 2022 16:50:32 -0700 Subject: [PATCH] [engine] fixed a few bugs --- openfpga/src/repack/repack.cpp | 10 +++++++++- openfpga/src/repack/repack_option.cpp | 17 ++++++++++++----- ..._global_nets_on_pins_example_script.openfpga | 2 +- 3 files changed, 22 insertions(+), 7 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 2322dcca0..97cade1f7 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -440,6 +440,7 @@ void add_lb_router_nets(LbRouter& lb_router, /* Cache the sink nodes/routing traces for the global nets which is specifed to be ignored on given pins */ std::map> ignored_global_net_sinks; + std::map ignored_atom_nets; for (int j = 0; j < lb_type->pb_type->num_pins; j++) { /* Get the source pb_graph pin and find the rr_node in logical block routing resource graph */ const t_pb_graph_pin* source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, j); @@ -481,6 +482,7 @@ void add_lb_router_nets(LbRouter& lb_router, std::vector sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation); VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size()); ignored_global_net_sinks[atom_net_id].insert(ignored_global_net_sinks[atom_net_id].end(), sink_lb_rr_nodes.begin(), sink_lb_rr_nodes.end()); + ignored_atom_nets[atom_net_id] = true; } } @@ -507,6 +509,12 @@ void add_lb_router_nets(LbRouter& lb_router, /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; + BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); + if ( (ignored_atom_nets[atom_net_id]) + && (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), curr_pin))) { + continue; + } + /* Check if the net information is constrained or not */ std::string constrained_net_name = design_constraints.find_constrained_pin_net(std::string(lb_type->pb_type->name), BasicPort(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number)); @@ -622,7 +630,7 @@ void add_lb_router_nets(LbRouter& lb_router, /* Append sink nodes from ignored global net cache */ sink_lb_rr_nodes.insert(sink_lb_rr_nodes.end(), ignored_global_net_sinks[atom_net_id_to_route].begin(), ignored_global_net_sinks[atom_net_id_to_route].end()); - VTR_LOGV(verbose, "Append %ld sinks from the routing traces of ignored global nets\n", ignored_global_net_sinks.size()); + VTR_LOGV(verbose, "Append %ld sinks from the routing traces of ignored global nets\n", ignored_global_net_sinks[atom_net_id_to_route].size()); /* Add the net */ add_lb_router_net_to_route(lb_router, lb_rr_graph, diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index 96b79b860..13b3b54ce 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -68,7 +68,7 @@ void RepackOption::set_ignore_global_nets_on_pins(const std::string& content) { std::vector pin_info = pin_tokenizer.split('.'); /* Expect two contents, otherwise error out */ if (pin_info.size() != 2) { - std::string err_msg = std::string("Invalid content '") + token + std::string("' to skip, expect ."); + std::string err_msg = std::string("Invalid content '") + token + std::string("' to skip, expect .\n"); VTR_LOG_ERROR(err_msg.c_str()); num_parse_errors_++; continue; @@ -77,7 +77,7 @@ void RepackOption::set_ignore_global_nets_on_pins(const std::string& content) { PortParser port_parser(pin_info[1]); BasicPort curr_port = port_parser.port(); if (!curr_port.is_valid()) { - std::string err_msg = std::string("Invalid pin definition '") + token + std::string("', expect .[int:int]"); + std::string err_msg = std::string("Invalid pin definition '") + token + std::string("', expect .[int:int]\n"); VTR_LOG_ERROR(err_msg.c_str()); num_parse_errors_++; continue; @@ -87,21 +87,28 @@ void RepackOption::set_ignore_global_nets_on_pins(const std::string& content) { auto result = ignore_global_nets_on_pins_.find(pb_type_name); if (result == ignore_global_nets_on_pins_.end()) { /* Not found, push the port */ - result->second.push_back(curr_port); + ignore_global_nets_on_pins_[pb_type_name].push_back(curr_port); } else { /* Already a list of ports. Check one by one. * - It already contained, do nothing but throw a warning. * - If we can merge, merge it. * - Otherwise, create it */ + bool included_by_existing_port = false; for (BasicPort existing_port : result->second) { if (existing_port.mergeable(curr_port)) { if (!existing_port.contained(curr_port)) { result->second.push_back(curr_port); + included_by_existing_port = true; + break; + } else { + std::string warn_msg = std::string("Pin definition '") + token + std::string("' is already included by other pin\n"); + VTR_LOG_WARN(warn_msg.c_str()); } - } else { - result->second.push_back(curr_port); } } + if (!included_by_existing_port) { + result->second.push_back(curr_port); + } } } } diff --git a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga index 5144cbc21..707371a80 100644 --- a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga @@ -33,7 +33,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation # Strongly recommend it is done after all the fix-up have been applied -repack --ignore_global_nets_on_pins clb.I #--verbose +repack --ignore_global_nets_on_pins clb.I[0:11] #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file