diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index 4e1b3b1cf..e566c8fb7 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -212,11 +212,16 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
 
       /* For bus ports, include a complete list of pins */
       BusGroupId bus_id = bus_group.find_bus(port_names[iport]);
+
       if (bus_id) {
         fp << "{";
         int pin_counter = 0;
-        /* Include all the pins */
-        for (const BusPinId& pin : bus_group.bus_pins(bus_id)) {
+        /* Include all the pins: If it follows little endian, reverse the pin sequence */
+        std::vector<BusPinId> bus_pins = bus_group.bus_pins(bus_id);
+        if (!bus_group.is_big_endian(bus_id)) {
+          std::reverse(bus_pins.begin(), bus_pins.end());
+        }
+        for (const BusPinId& pin : bus_pins) {
           if (0 < pin_counter) {
             fp << ", ";
           }