diff --git a/libs/libopenfpgashell/src/shell.h b/libs/libopenfpgashell/src/shell.h index 22ec81e0f..d209f38b4 100644 --- a/libs/libopenfpgashell/src/shell.h +++ b/libs/libopenfpgashell/src/shell.h @@ -65,13 +65,23 @@ class Shell { * Built-in commands have their own execute functions inside the shell */ enum e_exec_func_type { - CONST_STANDARD, - STANDARD, - CONST_SHORT, - SHORT, - BUILTIN, - MACRO, - WRAPPER, + CONST_STANDARD, /* A standard function requires to read data from the + command context, need the shell to provide command + parsing */ + STANDARD, /* A standard function requires to write data to the command + context, need the shell to provide command parsing */ + CONST_SHORT, /* A short function requries to read data from the common + context without any command-line options */ + SHORT, /* A short function requries to write data to the common context + without any command-line options */ + BUILTIN, /* A built-in function which requires no input arguments at all */ + FLOATING, /* A floating function which does not need to write/read any data + from the common context. Need shell to provide command parsing + */ + MACRO, /* A black-box function which has its own command-line + parser/interface. No need for shell to provide command parsing */ + PLUGIN, /* A plug-in function which is based on other commands, require + shell methods */ NUM_EXEC_FUNC_TYPES }; @@ -99,7 +109,8 @@ class Shell { public: /* Public mutators */ void set_name(const char* name); void add_title(const char* title); - ShellCommandId add_command(const Command& cmd, const char* descr); + ShellCommandId add_command(const Command& cmd, const char* descr, + const bool& hidden = false); void set_command_class(const ShellCommandId& cmd_id, const ShellCommandClassId& cmd_class_id); /* Link the execute function to a command @@ -150,12 +161,20 @@ class Shell { void set_command_execute_function(const ShellCommandId& cmd_id, std::function exec_func); + /* Floating function, including the only commands + * This is designed for implementing functions which is totally independent + * from + */ + void set_command_execute_function( + const ShellCommandId& cmd_id, + std::function exec_func); + /* Marco function, which directly call a macro function without command * parsing */ void set_command_execute_function(const ShellCommandId& cmd_id, std::function exec_func); - /* Wrapper function, which calls other command thru shell's APIs */ + /* Plug-in function, which calls other command thru shell's APIs */ void set_command_execute_function( const ShellCommandId& cmd_id, std::function*, T&, const Command&, const CommandContext&)> @@ -178,7 +197,7 @@ class Shell { void run_script_mode(const char* script_file_name, T& context, const bool& batch_mode = false); /* Print all the commands by their classes. This is actually the help desk */ - void print_commands() const; + void print_commands(const bool& show_hidden = false) const; /* Find the exit code (assume quit shell now) */ int exit_code() const; /* Show statistics of errors during command execution */ @@ -207,6 +226,9 @@ class Shell { /* Unique ids for each command */ vtr::vector command_ids_; + /* If this is a hidden command which will not appear in help desk */ + vtr::vector command_hidden_; + /* Objects for each command */ vtr::vector commands_; @@ -238,13 +260,16 @@ class Shell { command_short_const_execute_functions_; vtr::vector> command_short_execute_functions_; + vtr::vector> + command_floating_execute_functions_; vtr::vector> command_builtin_execute_functions_; vtr::vector> command_macro_execute_functions_; vtr::vector*, T&, const Command&, const CommandContext&)>> - command_wrapper_execute_functions_; + command_plugin_execute_functions_; /* Type of execute functions for each command. * This is supposed to be an internal data ONLY diff --git a/libs/libopenfpgashell/src/shell.tpp b/libs/libopenfpgashell/src/shell.tpp index 0426b5949..3afeef4b6 100644 --- a/libs/libopenfpgashell/src/shell.tpp +++ b/libs/libopenfpgashell/src/shell.tpp @@ -116,7 +116,7 @@ void Shell::add_title(const char* title) { /* Add a command with it description */ template -ShellCommandId Shell::add_command(const Command& cmd, const char* descr) { +ShellCommandId Shell::add_command(const Command& cmd, const char* descr, const bool& hidden) { /* Ensure that the name is unique in the command list */ std::map::const_iterator name_it = command_name2ids_.find(std::string(cmd.name())); if (name_it != command_name2ids_.end()) { @@ -126,6 +126,7 @@ ShellCommandId Shell::add_command(const Command& cmd, const char* descr) { /* This is a legal name. we can create a new id */ ShellCommandId shell_cmd = ShellCommandId(command_ids_.size()); command_ids_.push_back(shell_cmd); + command_hidden_.push_back(hidden); commands_.emplace_back(cmd); command_contexts_.push_back(CommandContext(cmd)); command_description_.push_back(descr); @@ -136,7 +137,8 @@ ShellCommandId Shell::add_command(const Command& cmd, const char* descr) { command_short_const_execute_functions_.emplace_back(); command_short_execute_functions_.emplace_back(); command_builtin_execute_functions_.emplace_back(); - command_wrapper_execute_functions_.emplace_back(); + command_plugin_execute_functions_.emplace_back(); + command_floating_execute_functions_.emplace_back(); command_macro_execute_functions_.emplace_back(); command_status_.push_back(CMD_EXEC_NONE); /* By default, the command should be marked as fatal error as it has been never executed */ command_dependencies_.emplace_back(); @@ -212,8 +214,16 @@ template void Shell::set_command_execute_function(const ShellCommandId& cmd_id, std::function*, T&, const Command&, const CommandContext&)> exec_func) { VTR_ASSERT(true == valid_command_id(cmd_id)); - command_execute_function_types_[cmd_id] = WRAPPER; - command_wrapper_execute_functions_[cmd_id] = exec_func; + command_execute_function_types_[cmd_id] = PLUGIN; + command_plugin_execute_functions_[cmd_id] = exec_func; +} + +template +void Shell::set_command_execute_function(const ShellCommandId& cmd_id, + std::function exec_func) { + VTR_ASSERT(true == valid_command_id(cmd_id)); + command_execute_function_types_[cmd_id] = FLOATING; + command_floating_execute_functions_[cmd_id] = exec_func; } template @@ -397,16 +407,28 @@ void Shell::run_script_mode(const char* script_file_name, } template -void Shell::print_commands() const { +void Shell::print_commands(const bool& show_hidden) const { /* Print the commands by their classes */ for (const ShellCommandClassId& cmd_class : command_class_ids_) { + /* If there are only hidden commands inside, do not even need to show the class name here */ + bool hidden_class = true; + for (const ShellCommandId& cmd : commands_by_classes_[cmd_class]) { + if (!command_hidden_[cmd]) { + hidden_class = false; + break; + } + } + /* Print the class name */ + if (show_hidden && hidden_class) { + continue; + } VTR_LOG("%s:\n", command_class_names_[cmd_class].c_str()); for (const ShellCommandId& cmd : commands_by_classes_[cmd_class]) { - /* Print the command names in this class - * but limited4 command per line for a clean layout - */ + if (show_hidden && command_hidden_[cmd]) { + continue; + } VTR_LOG("\t%s\n", commands_[cmd].name().c_str()); } @@ -568,8 +590,8 @@ int Shell::execute_command(const char* cmd_line, /* Execute the command depending on the type of function ! */ switch (command_execute_function_types_[cmd_id]) { - case WRAPPER: - command_status_[cmd_id] = command_wrapper_execute_functions_[cmd_id](this, common_context, commands_[cmd_id], command_contexts_[cmd_id]); + case PLUGIN: + command_status_[cmd_id] = command_plugin_execute_functions_[cmd_id](this, common_context, commands_[cmd_id], command_contexts_[cmd_id]); break; case CONST_STANDARD: command_status_[cmd_id] = command_const_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]); @@ -577,6 +599,9 @@ int Shell::execute_command(const char* cmd_line, case STANDARD: command_status_[cmd_id] = command_standard_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]); break; + case FLOATING: + command_status_[cmd_id] = command_floating_execute_functions_[cmd_id](commands_[cmd_id], command_contexts_[cmd_id]); + break; case CONST_SHORT: command_status_[cmd_id] = command_short_const_execute_functions_[cmd_id](common_context); break; diff --git a/openfpga/src/annotation/check_netlist_naming_conflict.cpp b/openfpga/src/annotation/check_netlist_naming_conflict.cpp index efc8a32d9..a686b055c 100644 --- a/openfpga/src/annotation/check_netlist_naming_conflict.cpp +++ b/openfpga/src/annotation/check_netlist_naming_conflict.cpp @@ -80,8 +80,8 @@ static std::string fix_name_contain_sensitive_chars( * - Iterate over all the nets and see if any net name contain * any sensitive character *******************************************************************/ -static size_t detect_netlist_naming_conflict( - const AtomNetlist& atom_netlist, const std::string& sensitive_chars) { +size_t detect_netlist_naming_conflict(const AtomNetlist& atom_netlist, + const std::string& sensitive_chars) { size_t num_conflicts = 0; /* Walk through blocks in the netlist */ @@ -119,9 +119,10 @@ static size_t detect_netlist_naming_conflict( * - Iterate over all the nets and correct any net name that contains * any sensitive character *******************************************************************/ -static void fix_netlist_naming_conflict( - const AtomNetlist& atom_netlist, const std::string& sensitive_chars, - const std::string& fix_chars, VprNetlistAnnotation& vpr_netlist_annotation) { +void fix_netlist_naming_conflict(const AtomNetlist& atom_netlist, + const std::string& sensitive_chars, + const std::string& fix_chars, + VprNetlistAnnotation& vpr_netlist_annotation) { size_t num_fixes = 0; /* Walk through blocks in the netlist */ @@ -162,7 +163,7 @@ static void fix_netlist_naming_conflict( * Report all the fix-up in the naming of netlist components, * i.e., blocks, nets *******************************************************************/ -static void print_netlist_naming_fix_report( +void print_netlist_naming_fix_report( const std::string& fname, const AtomNetlist& atom_netlist, const VprNetlistAnnotation& vpr_netlist_annotation) { /* Create a file handler */ @@ -229,64 +230,4 @@ static void print_netlist_naming_fix_report( fp.close(); } -/******************************************************************** - * Top-level function to detect and correct any naming - * in the users' BLIF netlist that violates the syntax of OpenFPGA - * fabric generator, i.e., Verilog generator and SPICE generator - *******************************************************************/ -int check_netlist_naming_conflict(OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context) { - vtr::ScopedStartFinishTimer timer( - "Check naming violations of netlist blocks and nets"); - - /* By default, we replace all the illegal characters with '_' */ - const std::string& sensitive_chars(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/"); - const std::string& fix_chars("____________________________"); - - CommandOptionId opt_fix = cmd.option("fix"); - - /* Do the main job first: detect any naming in the BLIF netlist that violates - * the syntax */ - if (false == cmd_context.option_enable(cmd, opt_fix)) { - size_t num_conflicts = - detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); - VTR_LOGV_ERROR( - (0 < num_conflicts && (false == cmd_context.option_enable(cmd, opt_fix))), - "Found %ld naming conflicts in the netlist. Please correct so as to use " - "any fabric generators.\n", - num_conflicts); - VTR_LOGV(0 == num_conflicts, - "Check naming conflicts in the netlist passed.\n"); - - /* If we see conflicts, report minor error */ - if (0 < num_conflicts) { - return CMD_EXEC_MINOR_ERROR; - } - - /* Otherwise, we should see zero conflicts */ - VTR_ASSERT(0 == num_conflicts); - return CMD_EXEC_SUCCESS; - } - - /* If the auto correction is enabled, we apply a fix */ - if (true == cmd_context.option_enable(cmd, opt_fix)) { - fix_netlist_naming_conflict( - g_vpr_ctx.atom().nlist, sensitive_chars, fix_chars, - openfpga_context.mutable_vpr_netlist_annotation()); - - CommandOptionId opt_report = cmd.option("report"); - if (true == cmd_context.option_enable(cmd, opt_report)) { - print_netlist_naming_fix_report( - cmd_context.option_value(cmd, opt_report), g_vpr_ctx.atom().nlist, - openfpga_context.vpr_netlist_annotation()); - VTR_LOG("Naming fix-up report is generated to file '%s'\n", - cmd_context.option_value(cmd, opt_report).c_str()); - } - } - - /* TODO: should identify the error code from internal function execution */ - return CMD_EXEC_SUCCESS; -} - } /* end namespace openfpga */ diff --git a/openfpga/src/annotation/check_netlist_naming_conflict.h b/openfpga/src/annotation/check_netlist_naming_conflict.h index 1dc064117..41ae16307 100644 --- a/openfpga/src/annotation/check_netlist_naming_conflict.h +++ b/openfpga/src/annotation/check_netlist_naming_conflict.h @@ -4,9 +4,12 @@ /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ +#include + +#include "atom_netlist.h" #include "command.h" #include "command_context.h" -#include "openfpga_context.h" +#include "vpr_netlist_annotation.h" /******************************************************************** * Function declaration @@ -15,9 +18,17 @@ /* begin namespace openfpga */ namespace openfpga { -int check_netlist_naming_conflict(OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context); +size_t detect_netlist_naming_conflict(const AtomNetlist& atom_netlist, + const std::string& sensitive_chars); + +void fix_netlist_naming_conflict(const AtomNetlist& atom_netlist, + const std::string& sensitive_chars, + const std::string& fix_chars, + VprNetlistAnnotation& vpr_netlist_annotation); + +void print_netlist_naming_fix_report( + const std::string& fname, const AtomNetlist& atom_netlist, + const VprNetlistAnnotation& vpr_netlist_annotation); } /* end namespace openfpga */ diff --git a/openfpga/src/annotation/check_netlist_naming_conflict_template.h b/openfpga/src/annotation/check_netlist_naming_conflict_template.h new file mode 100644 index 000000000..8b9886003 --- /dev/null +++ b/openfpga/src/annotation/check_netlist_naming_conflict_template.h @@ -0,0 +1,83 @@ +#ifndef CHECK_NETLIST_NAMING_CONFLICT_TEMPLATE_H +#define CHECK_NETLIST_NAMING_CONFLICT_TEMPLATE_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "check_netlist_naming_conflict.h" +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "vtr_time.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Top-level function to detect and correct any naming + * in the users' BLIF netlist that violates the syntax of OpenFPGA + * fabric generator, i.e., Verilog generator and SPICE generator + *******************************************************************/ +template +int check_netlist_naming_conflict_template(T& openfpga_context, + const Command& cmd, + const CommandContext& cmd_context) { + vtr::ScopedStartFinishTimer timer( + "Check naming violations of netlist blocks and nets"); + + /* By default, we replace all the illegal characters with '_' */ + std::string sensitive_chars(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/"); + std::string fix_chars("____________________________"); + + CommandOptionId opt_fix = cmd.option("fix"); + + /* Do the main job first: detect any naming in the BLIF netlist that violates + * the syntax */ + if (false == cmd_context.option_enable(cmd, opt_fix)) { + size_t num_conflicts = + detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); + VTR_LOGV_ERROR( + (0 < num_conflicts && (false == cmd_context.option_enable(cmd, opt_fix))), + "Found %ld naming conflicts in the netlist. Please correct so as to use " + "any fabric generators.\n", + num_conflicts); + VTR_LOGV(0 == num_conflicts, + "Check naming conflicts in the netlist passed.\n"); + + /* If we see conflicts, report minor error */ + if (0 < num_conflicts) { + return CMD_EXEC_MINOR_ERROR; + } + + /* Otherwise, we should see zero conflicts */ + VTR_ASSERT(0 == num_conflicts); + return CMD_EXEC_SUCCESS; + } + + /* If the auto correction is enabled, we apply a fix */ + if (true == cmd_context.option_enable(cmd, opt_fix)) { + fix_netlist_naming_conflict( + g_vpr_ctx.atom().nlist, sensitive_chars, fix_chars, + openfpga_context.mutable_vpr_netlist_annotation()); + + CommandOptionId opt_report = cmd.option("report"); + if (true == cmd_context.option_enable(cmd, opt_report)) { + print_netlist_naming_fix_report( + cmd_context.option_value(cmd, opt_report), g_vpr_ctx.atom().nlist, + openfpga_context.vpr_netlist_annotation()); + VTR_LOG("Naming fix-up report is generated to file '%s'\n", + cmd_context.option_value(cmd, opt_report).c_str()); + } + } + + /* TODO: should identify the error code from internal function execution */ + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/basic_command.cpp b/openfpga/src/base/basic_command.cpp index 52d540b41..73a9a2936 100644 --- a/openfpga/src/base/basic_command.cpp +++ b/openfpga/src/base/basic_command.cpp @@ -114,6 +114,14 @@ void add_basic_commands(openfpga::Shell& shell) { shell.set_command_execute_function(shell_cmd_version_id, print_openfpga_version_info); + /* Add a hidden command: internal_version */ + Command shell_cmd_internal_version("hidden_version"); + ShellCommandId shell_cmd_internal_version_id = shell.add_command( + shell_cmd_internal_version, "Show internal version information", true); + shell.set_command_class(shell_cmd_internal_version_id, basic_cmd_class); + shell.set_command_execute_function(shell_cmd_internal_version_id, + print_openfpga_version_info); + /* Add 'source' command which can run a set of commands */ add_openfpga_source_command(shell, basic_cmd_class, std::vector()); diff --git a/openfpga/src/base/openfpga_bitstream.h b/openfpga/src/base/openfpga_bitstream.h deleted file mode 100644 index 8934aac77..000000000 --- a/openfpga/src/base/openfpga_bitstream.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef OPENFPGA_BITSTREAM_H -#define OPENFPGA_BITSTREAM_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int fpga_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -int write_io_mapping(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp index 796356731..e3e90b8d6 100644 --- a/openfpga/src/base/openfpga_bitstream_command.cpp +++ b/openfpga/src/base/openfpga_bitstream_command.cpp @@ -6,330 +6,16 @@ *******************************************************************/ #include "openfpga_bitstream_command.h" -#include "openfpga_bitstream.h" -#include "openfpga_repack.h" +#include "openfpga_bitstream_command_template.h" /* begin namespace openfpga */ namespace openfpga { -/******************************************************************** - * - Add a command to Shell environment: repack - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_repack_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("repack"); - - /* Add an option '--design_constraints' */ - CommandOptionId opt_design_constraints = shell_cmd.add_option( - "design_constraints", false, "file path to the design constraints"); - shell_cmd.set_option_require_value(opt_design_constraints, - openfpga::OPT_STRING); - - /* Add an option '--ignore_global_nets_on_pins' */ - CommandOptionId opt_ignore_global_nets = - shell_cmd.add_option("ignore_global_nets_on_pins", false, - "Specify the pins where global nets will be ignored. " - "Routing traces are merged to other pins"); - shell_cmd.set_option_require_value(opt_ignore_global_nets, - openfpga::OPT_STRING); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'repack' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "Pack physical programmable logic blocks"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, repack); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: build_architecture_bitstream - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_build_arch_bitstream_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("build_architecture_bitstream"); - - /* Add an option '--write_file' */ - CommandOptionId opt_write_file = shell_cmd.add_option( - "write_file", false, "file path to output the bitstream database"); - shell_cmd.set_option_require_value(opt_write_file, openfpga::OPT_STRING); - - /* Add an option '--read_file' */ - CommandOptionId opt_read_file = shell_cmd.add_option( - "read_file", false, "file path to read the bitstream database"); - shell_cmd.set_option_require_value(opt_read_file, openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'build_architecture_bitstream' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "Build fabric-independent bitstream database"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, fpga_bitstream); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: report_bitstream_distribution - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_report_bitstream_distribution_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("report_bitstream_distribution"); - - /* Add an option '--file' */ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "file path to output the bitstream distribution"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add an option '--depth' */ - CommandOptionId opt_depth = shell_cmd.add_option( - "depth", false, - "Specify the max. depth of blocks which will appear in report"); - shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'report_bitstream_distribution' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "Report bitstream distribution"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, - report_bitstream_distribution); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: build_fabric_bitstream - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_build_fabric_bitstream_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("build_fabric_bitstream"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'fabric_bitstream' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, - "Reorganize the fabric-independent bitstream for the " - "FPGA fabric created by FPGA-Verilog"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, build_fabric_bitstream); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_fabric_bitstream - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_fabric_bitstream_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_fabric_bitstream"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, - "file path to output the fabric bitstream to plain text file"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add an option '--file_format'*/ - CommandOptionId opt_file_format = shell_cmd.add_option( - "format", false, - "file format of fabric bitstream [plain_text|xml]. Default: plain_text"); - shell_cmd.set_option_require_value(opt_file_format, openfpga::OPT_STRING); - - /* Add an option '--fast_configuration' */ - shell_cmd.add_option("fast_configuration", false, - "Reduce the size of bitstream to be downloaded"); - - /* Add an option '--keep_dont_care_bit' */ - shell_cmd.add_option( - "keep_dont_care_bits", false, - "Keep don't care bits in bitstream file; If not enabled, don't care bits " - "are converted to logic '0' or '1'"); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'fabric_bitstream' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "Write the fabric-dependent bitstream to a file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_fabric_bitstream); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_io_mapping - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_io_mapping_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_io_mapping"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "file path to output the io mapping information"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'fabric_bitstream' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "Write the I/O mapping information to a file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_io_mapping); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - /******************************************************************** * Top-level function to add all the commands related to FPGA-Bitstream *******************************************************************/ void add_openfpga_bitstream_commands(openfpga::Shell& shell) { - /* Get the unique id of 'build_fabric' command which is to be used in creating - * the dependency graph */ - const ShellCommandId& shell_cmd_build_fabric_id = - shell.command(std::string("build_fabric")); - - /* Add a new class of commands */ - ShellCommandClassId openfpga_bitstream_cmd_class = - shell.add_command_class("FPGA-Bitstream"); - - /******************************** - * Command 'repack' - */ - /* The 'repack' command should NOT be executed before 'build_fabric' */ - std::vector cmd_dependency_repack; - cmd_dependency_repack.push_back(shell_cmd_build_fabric_id); - ShellCommandId shell_cmd_repack_id = add_openfpga_repack_command( - shell, openfpga_bitstream_cmd_class, cmd_dependency_repack); - - /******************************** - * Command 'build_architecture_bitstream' - */ - /* The 'build_architecture_bitstream' command should NOT be executed before - * 'repack' */ - std::vector cmd_dependency_build_arch_bitstream; - cmd_dependency_build_arch_bitstream.push_back(shell_cmd_repack_id); - ShellCommandId shell_cmd_build_arch_bitstream_id = - add_openfpga_build_arch_bitstream_command( - shell, openfpga_bitstream_cmd_class, cmd_dependency_build_arch_bitstream); - - /******************************** - * Command 'report_bitstream_distribution' - */ - /* The 'report_bitstream_distribution' command should NOT be executed before - * 'build_architecture_bitstream' */ - std::vector cmd_dependency_report_bitstream_distribution; - cmd_dependency_build_arch_bitstream.push_back( - shell_cmd_build_arch_bitstream_id); - add_openfpga_report_bitstream_distribution_command( - shell, openfpga_bitstream_cmd_class, - cmd_dependency_report_bitstream_distribution); - - /******************************** - * Command 'build_fabric_bitstream' - */ - /* The 'build_fabric_bitstream' command should NOT be executed before - * 'build_architecture_bitstream' */ - std::vector cmd_dependency_build_fabric_bitstream; - cmd_dependency_build_fabric_bitstream.push_back( - shell_cmd_build_arch_bitstream_id); - ShellCommandId shell_cmd_build_fabric_bitstream_id = - add_openfpga_build_fabric_bitstream_command( - shell, openfpga_bitstream_cmd_class, - cmd_dependency_build_fabric_bitstream); - - /******************************** - * Command 'write_fabric_bitstream' - */ - /* The 'write_fabric_bitstream' command should NOT be executed before - * 'build_fabric_bitstream' */ - std::vector cmd_dependency_write_fabric_bitstream; - cmd_dependency_write_fabric_bitstream.push_back( - shell_cmd_build_fabric_bitstream_id); - add_openfpga_write_fabric_bitstream_command( - shell, openfpga_bitstream_cmd_class, cmd_dependency_write_fabric_bitstream); - - /******************************** - * Command 'write_io_mapping' - */ - /* The 'write_io_mapping' command should NOT be executed before 'build_fabric' - */ - std::vector cmd_dependency_write_io_mapping; - cmd_dependency_write_io_mapping.push_back(shell_cmd_build_fabric_id); - add_openfpga_write_io_mapping_command(shell, openfpga_bitstream_cmd_class, - cmd_dependency_write_io_mapping); + add_bitstream_command_templates(shell); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_bitstream_command_template.h b/openfpga/src/base/openfpga_bitstream_command_template.h new file mode 100644 index 000000000..b11c058cd --- /dev/null +++ b/openfpga/src/base/openfpga_bitstream_command_template.h @@ -0,0 +1,347 @@ +#ifndef OPENFPGA_BITSTREAM_COMMAND_TEMPLATE_H +#define OPENFPGA_BITSTREAM_COMMAND_TEMPLATE_H +/******************************************************************** + * Add commands to the OpenFPGA shell interface, + * in purpose of generate Verilog netlists modeling the full FPGA fabric + * This is one of the core engine of openfpga, including: + * - repack : create physical pbs and redo packing + *******************************************************************/ +#include "openfpga_bitstream_template.h" +#include "openfpga_repack_template.h" +#include "shell.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * - Add a command to Shell environment: repack + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_repack_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("repack"); + + /* Add an option '--design_constraints' */ + CommandOptionId opt_design_constraints = shell_cmd.add_option( + "design_constraints", false, "file path to the design constraints"); + shell_cmd.set_option_require_value(opt_design_constraints, + openfpga::OPT_STRING); + + /* Add an option '--ignore_global_nets_on_pins' */ + CommandOptionId opt_ignore_global_nets = + shell_cmd.add_option("ignore_global_nets_on_pins", false, + "Specify the pins where global nets will be ignored. " + "Routing traces are merged to other pins"); + shell_cmd.set_option_require_value(opt_ignore_global_nets, + openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'repack' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Pack physical programmable logic blocks", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, repack_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: build_architecture_bitstream + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_build_arch_bitstream_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("build_architecture_bitstream"); + + /* Add an option '--write_file' */ + CommandOptionId opt_write_file = shell_cmd.add_option( + "write_file", false, "file path to output the bitstream database"); + shell_cmd.set_option_require_value(opt_write_file, openfpga::OPT_STRING); + + /* Add an option '--read_file' */ + CommandOptionId opt_read_file = shell_cmd.add_option( + "read_file", false, "file path to read the bitstream database"); + shell_cmd.set_option_require_value(opt_read_file, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'build_architecture_bitstream' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Build fabric-independent bitstream database", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, fpga_bitstream_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: report_bitstream_distribution + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_report_bitstream_distribution_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("report_bitstream_distribution"); + + /* Add an option '--file' */ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "file path to output the bitstream distribution"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--depth' */ + CommandOptionId opt_depth = shell_cmd.add_option( + "depth", false, + "Specify the max. depth of blocks which will appear in report"); + shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'report_bitstream_distribution' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "Report bitstream distribution", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + report_bitstream_distribution_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: build_fabric_bitstream + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_build_fabric_bitstream_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("build_fabric_bitstream"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'fabric_bitstream' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "Reorganize the fabric-independent bitstream for the " + "FPGA fabric created by FPGA-Verilog", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + build_fabric_bitstream_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_fabric_bitstream + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_bitstream_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_fabric_bitstream"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, + "file path to output the fabric bitstream to plain text file"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--file_format'*/ + CommandOptionId opt_file_format = shell_cmd.add_option( + "format", false, + "file format of fabric bitstream [plain_text|xml]. Default: plain_text"); + shell_cmd.set_option_require_value(opt_file_format, openfpga::OPT_STRING); + + /* Add an option '--fast_configuration' */ + shell_cmd.add_option("fast_configuration", false, + "Reduce the size of bitstream to be downloaded"); + + /* Add an option '--keep_dont_care_bit' */ + shell_cmd.add_option( + "keep_dont_care_bits", false, + "Keep don't care bits in bitstream file; If not enabled, don't care bits " + "are converted to logic '0' or '1'"); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'fabric_bitstream' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Write the fabric-dependent bitstream to a file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_fabric_bitstream_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_io_mapping + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_io_mapping_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_io_mapping"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "file path to output the io mapping information"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'fabric_bitstream' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Write the I/O mapping information to a file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_io_mapping_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * Top-level function to add all the commands related to FPGA-Bitstream + *******************************************************************/ +template +void add_bitstream_command_templates(openfpga::Shell& shell, + const bool& hidden = false) { + /* Get the unique id of 'build_fabric' command which is to be used in creating + * the dependency graph */ + const ShellCommandId& shell_cmd_build_fabric_id = + shell.command(std::string("build_fabric")); + + /* Add a new class of commands */ + ShellCommandClassId openfpga_bitstream_cmd_class = + shell.add_command_class("FPGA-Bitstream"); + + /******************************** + * Command 'repack' + */ + /* The 'repack' command should NOT be executed before 'build_fabric' */ + std::vector cmd_dependency_repack; + cmd_dependency_repack.push_back(shell_cmd_build_fabric_id); + ShellCommandId shell_cmd_repack_id = add_repack_command_template( + shell, openfpga_bitstream_cmd_class, cmd_dependency_repack, hidden); + + /******************************** + * Command 'build_architecture_bitstream' + */ + /* The 'build_architecture_bitstream' command should NOT be executed before + * 'repack' */ + std::vector cmd_dependency_build_arch_bitstream; + cmd_dependency_build_arch_bitstream.push_back(shell_cmd_repack_id); + ShellCommandId shell_cmd_build_arch_bitstream_id = + add_build_arch_bitstream_command_template( + shell, openfpga_bitstream_cmd_class, cmd_dependency_build_arch_bitstream, + hidden); + + /******************************** + * Command 'report_bitstream_distribution' + */ + /* The 'report_bitstream_distribution' command should NOT be executed before + * 'build_architecture_bitstream' */ + std::vector cmd_dependency_report_bitstream_distribution; + cmd_dependency_build_arch_bitstream.push_back( + shell_cmd_build_arch_bitstream_id); + add_report_bitstream_distribution_command_template( + shell, openfpga_bitstream_cmd_class, + cmd_dependency_report_bitstream_distribution, hidden); + + /******************************** + * Command 'build_fabric_bitstream' + */ + /* The 'build_fabric_bitstream' command should NOT be executed before + * 'build_architecture_bitstream' */ + std::vector cmd_dependency_build_fabric_bitstream; + cmd_dependency_build_fabric_bitstream.push_back( + shell_cmd_build_arch_bitstream_id); + ShellCommandId shell_cmd_build_fabric_bitstream_id = + add_build_fabric_bitstream_command_template( + shell, openfpga_bitstream_cmd_class, + cmd_dependency_build_fabric_bitstream, hidden); + + /******************************** + * Command 'write_fabric_bitstream' + */ + /* The 'write_fabric_bitstream' command should NOT be executed before + * 'build_fabric_bitstream' */ + std::vector cmd_dependency_write_fabric_bitstream; + cmd_dependency_write_fabric_bitstream.push_back( + shell_cmd_build_fabric_bitstream_id); + add_write_fabric_bitstream_command_template( + shell, openfpga_bitstream_cmd_class, cmd_dependency_write_fabric_bitstream, + hidden); + + /******************************** + * Command 'write_io_mapping' + */ + /* The 'write_io_mapping' command should NOT be executed before 'build_fabric' + */ + std::vector cmd_dependency_write_io_mapping; + cmd_dependency_write_io_mapping.push_back(shell_cmd_build_fabric_id); + add_write_io_mapping_command_template(shell, openfpga_bitstream_cmd_class, + cmd_dependency_write_io_mapping, + hidden); +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream_template.h similarity index 88% rename from openfpga/src/base/openfpga_bitstream.cpp rename to openfpga/src/base/openfpga_bitstream_template.h index c95a18c0f..de01d1df9 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream_template.h @@ -1,41 +1,37 @@ +#ifndef OPENFPGA_BITSTREAM_TEMPLATE_H +#define OPENFPGA_BITSTREAM_TEMPLATE_H + /******************************************************************** * This file includes functions to build bitstream database *******************************************************************/ -/* Headers from vtrutil library */ -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from openfpgautil library */ -#include "openfpga_digest.h" -#include "openfpga_reserved_words.h" - -/* Headers from fpgabitstream library */ #include "build_device_bitstream.h" #include "build_fabric_bitstream.h" #include "build_io_mapping_info.h" -#include "openfpga_bitstream.h" +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "globals.h" +#include "openfpga_digest.h" #include "openfpga_naming.h" +#include "openfpga_reserved_words.h" #include "read_xml_arch_bitstream.h" #include "report_bitstream_distribution.h" +#include "vtr_log.h" +#include "vtr_time.h" #include "write_text_fabric_bitstream.h" #include "write_xml_arch_bitstream.h" #include "write_xml_fabric_bitstream.h" #include "write_xml_io_mapping.h" -/* Include global variables of VPR */ -#include "globals.h" - /* begin namespace openfpga */ namespace openfpga { /******************************************************************** * A wrapper function to call the build_device_bitstream() in FPGA bitstream *******************************************************************/ -int fpga_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int fpga_bitstream_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); CommandOptionId opt_write_file = cmd.option("write_file"); @@ -69,8 +65,9 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, /******************************************************************** * A wrapper function to call the build_fabric_bitstream() in FPGA bitstream *******************************************************************/ -int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int build_fabric_bitstream_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); /* Build fabric bitstream here */ @@ -86,9 +83,9 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, /******************************************************************** * A wrapper function to call the write_fabric_bitstream() in FPGA bitstream *******************************************************************/ -int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_fabric_bitstream_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_file = cmd.option("file"); CommandOptionId opt_file_format = cmd.option("format"); @@ -140,8 +137,9 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, /******************************************************************** * A wrapper function to call the write_io_mapping() in FPGA bitstream *******************************************************************/ -int write_io_mapping(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int write_io_mapping_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); CommandOptionId opt_file = cmd.option("file"); @@ -187,9 +185,10 @@ int write_io_mapping(const OpenfpgaContext& openfpga_ctx, const Command& cmd, * A wrapper function to call the report_arch_bitstream_distribution() in FPGA *bitstream *******************************************************************/ -int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int report_bitstream_distribution_template(const T& openfpga_ctx, + const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_file = cmd.option("file"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); @@ -225,3 +224,5 @@ int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_build_fabric.h b/openfpga/src/base/openfpga_build_fabric.h deleted file mode 100644 index db295edaf..000000000 --- a/openfpga/src/base/openfpga_build_fabric.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef OPENFPGA_BUILD_FABRIC_H -#define OPENFPGA_BUILD_FABRIC_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int build_fabric(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int write_fabric_hierarchy(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -int write_fabric_io_info(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric_template.h similarity index 89% rename from openfpga/src/base/openfpga_build_fabric.cpp rename to openfpga/src/base/openfpga_build_fabric_template.h index 3c6194aab..a42b51533 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -1,26 +1,22 @@ +#ifndef OPENFPGA_BUILD_FABRIC_TEMPLATE_H +#define OPENFPGA_BUILD_FABRIC_TEMPLATE_H /******************************************************************** * This file includes functions to compress the hierachy of routing architecture *******************************************************************/ -/* Headers from vtrutil library */ -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from fabrickey library */ #include "build_device_module.h" #include "build_fabric_global_port_info.h" #include "build_fabric_io_location_map.h" +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" #include "device_rr_gsb.h" #include "device_rr_gsb_utils.h" #include "fabric_hierarchy_writer.h" #include "fabric_key_writer.h" -#include "openfpga_build_fabric.h" -#include "read_xml_fabric_key.h" - -/* Include global variables of VPR */ #include "globals.h" +#include "read_xml_fabric_key.h" +#include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { @@ -29,8 +25,9 @@ namespace openfpga { * Identify the unique GSBs from the Device RR GSB arrays * This function should only be called after the GSB builder is done *******************************************************************/ -static void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx, - const bool& verbose_output) { +template +void compress_routing_hierarchy_template(T& openfpga_ctx, + const bool& verbose_output) { vtr::ScopedStartFinishTimer timer( "Identify unique General Switch Blocks (GSBs)"); @@ -88,8 +85,9 @@ static void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx, /******************************************************************** * Build the module graph for FPGA device *******************************************************************/ -int build_fabric(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int build_fabric_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_frame_view = cmd.option("frame_view"); CommandOptionId opt_compress_routing = cmd.option("compress_routing"); CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin"); @@ -100,8 +98,8 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, const Command& cmd, CommandOptionId opt_verbose = cmd.option("verbose"); if (true == cmd_context.option_enable(cmd, opt_compress_routing)) { - compress_routing_hierarchy(openfpga_ctx, - cmd_context.option_enable(cmd, opt_verbose)); + compress_routing_hierarchy_template( + openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } @@ -127,7 +125,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, const Command& cmd, curr_status = build_device_module_graph( openfpga_ctx.mutable_module_graph(), openfpga_ctx.mutable_decoder_lib(), openfpga_ctx.mutable_blwl_shift_register_banks(), - const_cast(openfpga_ctx), g_vpr_ctx.device(), + const_cast(openfpga_ctx), g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_frame_view), cmd_context.option_enable(cmd, opt_compress_routing), cmd_context.option_enable(cmd, opt_duplicate_grid_pin), @@ -174,9 +172,9 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, const Command& cmd, /******************************************************************** * Write hierarchy of the module graph for FPGA device to a file *******************************************************************/ -int write_fabric_hierarchy(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); /* Check the option '--file' is enabled or not @@ -211,9 +209,9 @@ int write_fabric_hierarchy(const OpenfpgaContext& openfpga_ctx, /******************************************************************** * Write the I/O information of module graph to a file *******************************************************************/ -int write_fabric_io_info(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_fabric_io_info_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); @@ -234,3 +232,5 @@ int write_fabric_io_info(const OpenfpgaContext& openfpga_ctx, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_link_arch.h b/openfpga/src/base/openfpga_link_arch.h deleted file mode 100644 index f2f66f941..000000000 --- a/openfpga/src/base/openfpga_link_arch.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef OPENFPGA_LINK_ARCH_H -#define OPENFPGA_LINK_ARCH_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int link_arch(OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch_template.h similarity index 82% rename from openfpga/src/base/openfpga_link_arch.cpp rename to openfpga/src/base/openfpga_link_arch_template.h index 9c2b666b0..9dbb1893f 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -1,17 +1,9 @@ +#ifndef OPENFPGA_LINK_ARCH_TEMPLATE_H +#define OPENFPGA_LINK_ARCH_TEMPLATE_H /******************************************************************** * This file includes functions to read an OpenFPGA architecture file * which are built on the libarchopenfpga library *******************************************************************/ - -/* Headers from vtrutil library */ -#include "vtr_assert.h" -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from vpr library */ #include "annotate_bitstream_setting.h" #include "annotate_clustering.h" #include "annotate_pb_graph.h" @@ -21,50 +13,23 @@ #include "annotate_rr_graph.h" #include "annotate_simulation_setting.h" #include "build_tile_direct.h" +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "globals.h" #include "mux_library_builder.h" #include "openfpga_annotate_routing.h" -#include "openfpga_link_arch.h" +#include "openfpga_rr_graph_support.h" #include "pb_type_utils.h" #include "read_activity.h" #include "vpr_device_annotation.h" - -/* Include global variables of VPR */ -#include "globals.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { -/******************************************************************** - * A function to identify if the routing resource graph generated by - * VPR is support by OpenFPGA - * - Currently we only support uni-directional - * It means every routing tracks must have a direction - *******************************************************************/ -static bool is_vpr_rr_graph_supported(const RRGraphView& rr_graph) { - /* Check if the rr_graph is uni-directional*/ - for (const RRNodeId& node : rr_graph.nodes()) { - if (CHANX != rr_graph.node_type(node) && - CHANY != rr_graph.node_type(node)) { - continue; - } - if (Direction::BIDIR == rr_graph.node_direction(node)) { - VTR_LOG_ERROR( - "Routing resource graph is bi-directional. OpenFPGA currently supports " - "uni-directional routing architecture only.\n"); - return false; - } - if (Direction::NONE == rr_graph.node_direction(node)) { - VTR_LOG_ERROR( - "Routing resource graph contains routing tracks which has not specific " - "direction. OpenFPGA currently supports uni-directional routing " - "architecture only.\n"); - return false; - } - } - - return true; -} - /******************************************************************** * Top-level function to link openfpga architecture to VPR, including: * - physical pb_type @@ -73,8 +38,9 @@ static bool is_vpr_rr_graph_supported(const RRGraphView& rr_graph) { * - physical pb_graph nodes and pb_graph pins * - circuit models for global routing architecture *******************************************************************/ -int link_arch(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int link_arch_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { vtr::ScopedStartFinishTimer timer( "Link OpenFPGA architecture to VPR architecture"); @@ -155,7 +121,7 @@ int link_arch(OpenfpgaContext& openfpga_ctx, const Command& cmd, /* Build multiplexer library */ openfpga_ctx.mutable_mux_lib() = build_device_mux_library( - g_vpr_ctx.device(), const_cast(openfpga_ctx)); + g_vpr_ctx.device(), const_cast(openfpga_ctx)); /* Build tile direct annotation */ openfpga_ctx.mutable_tile_direct() = build_device_tile_direct( @@ -217,3 +183,5 @@ int link_arch(OpenfpgaContext& openfpga_ctx, const Command& cmd, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp index 2f846e592..dacd6d131 100644 --- a/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp +++ b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp @@ -7,9 +7,6 @@ #include "vtr_log.h" #include "vtr_time.h" -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - /* Headers from vpr library */ #include "lut_utils.h" #include "openfpga_lut_truth_table_fixup.h" @@ -176,7 +173,7 @@ static void rec_adapt_lut_pb_tt( * Main function to fix up truth table for each LUT used in FPGA * This function will walk through each clustered block *******************************************************************/ -static void update_lut_tt_with_post_packing_results( +void update_lut_tt_with_post_packing_results( const AtomContext& atom_ctx, const ClusteringContext& clustering_ctx, VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose) { for (auto blk_id : clustering_ctx.clb_nlist.blocks()) { @@ -186,32 +183,4 @@ static void update_lut_tt_with_post_packing_results( } } -/******************************************************************** - * Top-level function to fix up the lut truth table results after packing is - *done The problem comes from a mismatch between the packing results and - * original truth tables in users' BLIF file - * As LUT inputs are equivalent in nature, the router of packer will try - * to swap the net mapping among these pins so as to achieve best - * routing optimization. - * However, it will cause the original truth table out-of-date when packing is - *done. This function aims to fix the mess after packing so that the truth table - * can be synchronized - *******************************************************************/ -int lut_truth_table_fixup(OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context) { - vtr::ScopedStartFinishTimer timer( - "Fix up LUT truth tables after packing optimization"); - - CommandOptionId opt_verbose = cmd.option("verbose"); - - /* Apply fix-up to each packed block */ - update_lut_tt_with_post_packing_results( - g_vpr_ctx.atom(), g_vpr_ctx.clustering(), - openfpga_context.mutable_vpr_clustering_annotation(), - cmd_context.option_enable(cmd, opt_verbose)); - - /* TODO: should identify the error code from internal function execution */ - return CMD_EXEC_SUCCESS; -} - } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup.h b/openfpga/src/base/openfpga_lut_truth_table_fixup.h index 3914fb3ca..d51bf240d 100644 --- a/openfpga/src/base/openfpga_lut_truth_table_fixup.h +++ b/openfpga/src/base/openfpga_lut_truth_table_fixup.h @@ -15,8 +15,9 @@ /* begin namespace openfpga */ namespace openfpga { -int lut_truth_table_fixup(OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context); +void update_lut_tt_with_post_packing_results( + const AtomContext& atom_ctx, const ClusteringContext& clustering_ctx, + VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup_template.h b/openfpga/src/base/openfpga_lut_truth_table_fixup_template.h new file mode 100644 index 000000000..5d76d33ae --- /dev/null +++ b/openfpga/src/base/openfpga_lut_truth_table_fixup_template.h @@ -0,0 +1,52 @@ +#ifndef OPENFPGA_LUT_TRUTH_TABLE_FIXUP_TEMPLATE_H +#define OPENFPGA_LUT_TRUTH_TABLE_FIXUP_TEMPLATE_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "openfpga_context.h" +#include "openfpga_lut_truth_table_fixup.h" +#include "vtr_time.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Top-level function to fix up the lut truth table results after packing is + *done The problem comes from a mismatch between the packing results and + * original truth tables in users' BLIF file + * As LUT inputs are equivalent in nature, the router of packer will try + * to swap the net mapping among these pins so as to achieve best + * routing optimization. + * However, it will cause the original truth table out-of-date when packing is + *done. This function aims to fix the mess after packing so that the truth table + * can be synchronized + *******************************************************************/ +template +int lut_truth_table_fixup_template(T& openfpga_context, const Command& cmd, + const CommandContext& cmd_context) { + vtr::ScopedStartFinishTimer timer( + "Fix up LUT truth tables after packing optimization"); + + CommandOptionId opt_verbose = cmd.option("verbose"); + + /* Apply fix-up to each packed block */ + update_lut_tt_with_post_packing_results( + g_vpr_ctx.atom(), g_vpr_ctx.clustering(), + openfpga_context.mutable_vpr_clustering_annotation(), + cmd_context.option_enable(cmd, opt_verbose)); + + /* TODO: should identify the error code from internal function execution */ + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 6bc693eeb..0e55f8f9d 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -20,9 +20,6 @@ #include "openfpga_side_manager.h" #include "pb_type_utils.h" -/* Include global variables of VPR */ -#include "globals.h" - /* begin namespace openfpga */ namespace openfpga { @@ -185,7 +182,7 @@ static void update_cluster_pin_with_post_routing_results( * Main function to fix up the pb pin mapping results * This function will walk through each grid *******************************************************************/ -static void update_pb_pin_with_post_routing_results( +void update_pb_pin_with_post_routing_results( const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const PlacementContext& placement_ctx, const VprRoutingAnnotation& vpr_routing_annotation, @@ -247,33 +244,4 @@ static void update_pb_pin_with_post_routing_results( } } -/******************************************************************** - * Top-level function to fix up the pb pin mapping results - * The problem comes from a mismatch between the packing and routing results - * When there are equivalent input/output for any grids, router will try - * to swap the net mapping among these pins so as to achieve best - * routing optimization. - * However, it will cause the packing results out-of-date as the net mapping - * of each grid remain untouched once packing is done. - * This function aims to fix the mess after routing so that the net mapping - * can be synchronized - *******************************************************************/ -int pb_pin_fixup(OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context) { - vtr::ScopedStartFinishTimer timer( - "Fix up pb pin mapping results after routing optimization"); - - CommandOptionId opt_verbose = cmd.option("verbose"); - - /* Apply fix-up to each grid */ - update_pb_pin_with_post_routing_results( - g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.placement(), - openfpga_context.vpr_routing_annotation(), - openfpga_context.mutable_vpr_clustering_annotation(), - cmd_context.option_enable(cmd, opt_verbose)); - - /* TODO: should identify the error code from internal function execution */ - return CMD_EXEC_SUCCESS; -} - } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.h b/openfpga/src/base/openfpga_pb_pin_fixup.h index e7141ebdc..6afaa43d1 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.h +++ b/openfpga/src/base/openfpga_pb_pin_fixup.h @@ -4,9 +4,8 @@ /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ -#include "command.h" -#include "command_context.h" #include "openfpga_context.h" +#include "vpr_context.h" /******************************************************************** * Function declaration @@ -15,8 +14,11 @@ /* begin namespace openfpga */ namespace openfpga { -int pb_pin_fixup(OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context); +void update_pb_pin_with_post_routing_results( + const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, + const PlacementContext& placement_ctx, + const VprRoutingAnnotation& vpr_routing_annotation, + VprClusteringAnnotation& vpr_clustering_annotation, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_pb_pin_fixup_template.h b/openfpga/src/base/openfpga_pb_pin_fixup_template.h new file mode 100644 index 000000000..e28c99467 --- /dev/null +++ b/openfpga/src/base/openfpga_pb_pin_fixup_template.h @@ -0,0 +1,53 @@ +#ifndef OPENFPGA_PB_PIN_FIXUP_TEMPLATE_H +#define OPENFPGA_PB_PIN_FIXUP_TEMPLATE_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "globals.h" +#include "openfpga_pb_pin_fixup.h" +#include "vtr_time.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Top-level function to fix up the pb pin mapping results + * The problem comes from a mismatch between the packing and routing results + * When there are equivalent input/output for any grids, router will try + * to swap the net mapping among these pins so as to achieve best + * routing optimization. + * However, it will cause the packing results out-of-date as the net mapping + * of each grid remain untouched once packing is done. + * This function aims to fix the mess after routing so that the net mapping + * can be synchronized + *******************************************************************/ +template +int pb_pin_fixup_template(T& openfpga_context, const Command& cmd, + const CommandContext& cmd_context) { + vtr::ScopedStartFinishTimer timer( + "Fix up pb pin mapping results after routing optimization"); + + CommandOptionId opt_verbose = cmd.option("verbose"); + + /* Apply fix-up to each grid */ + update_pb_pin_with_post_routing_results( + g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.placement(), + openfpga_context.vpr_routing_annotation(), + openfpga_context.mutable_vpr_clustering_annotation(), + cmd_context.option_enable(cmd, opt_verbose)); + + /* TODO: should identify the error code from internal function execution */ + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_pcf2place.h b/openfpga/src/base/openfpga_pcf2place.h deleted file mode 100644 index 7b8eb1a62..000000000 --- a/openfpga/src/base/openfpga_pcf2place.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef OPENFPGA_PCF2PLACE_H -#define OPENFPGA_PCF2PLACE_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, - const Command& cmd, const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_pcf2place.cpp b/openfpga/src/base/openfpga_pcf2place_template.h similarity index 93% rename from openfpga/src/base/openfpga_pcf2place.cpp rename to openfpga/src/base/openfpga_pcf2place_template.h index c3b70e85c..4c430aaad 100644 --- a/openfpga/src/base/openfpga_pcf2place.cpp +++ b/openfpga/src/base/openfpga_pcf2place_template.h @@ -1,24 +1,20 @@ +#ifndef OPENFPGA_PCF2PLACE_TEMPLATE_H +#define OPENFPGA_PCF2PLACE_TEMPLATE_H /******************************************************************** * This file includes functions to build bitstream database *******************************************************************/ -/* Headers from vtrutil library */ -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from openfpgautil library */ -#include "openfpga_digest.h" - -/* Headers from pcf library */ #include "blif_head_reader.h" +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" #include "io_net_place.h" -#include "openfpga_pcf2place.h" +#include "openfpga_digest.h" #include "pcf2place.h" #include "pcf_reader.h" #include "read_csv_io_pin_table.h" #include "read_xml_io_location_map.h" +#include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { @@ -27,8 +23,9 @@ namespace openfpga { * Top-level function to convert a .pcf file to a .place file which * which VPR can force I/O placement *******************************************************************/ -int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, - const Command& cmd, const CommandContext& cmd_context) { +template +int pcf2place_wrapper_template(const Command& cmd, + const CommandContext& cmd_context) { /* todo: create a factory to produce this in the future*/ CommandOptionId opt_pcf = cmd.option("pcf"); CommandOptionId opt_blif = cmd.option("blif"); @@ -118,3 +115,5 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_read_arch.h b/openfpga/src/base/openfpga_read_arch.h deleted file mode 100644 index 1d1e8d230..000000000 --- a/openfpga/src/base/openfpga_read_arch.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef OPENFPGA_READ_ARCH_COMMAND_H -#define OPENFPGA_READ_ARCH_COMMAND_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int read_arch(OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context); - -int write_arch(const OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context); - -int read_simulation_setting(OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context); - -int write_simulation_setting(const OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context); - -int read_bitstream_setting(OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context); - -int write_bitstream_setting(const OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch_template.h similarity index 86% rename from openfpga/src/base/openfpga_read_arch.cpp rename to openfpga/src/base/openfpga_read_arch_template.h index 9c7f41a3e..d80ac6f84 100644 --- a/openfpga/src/base/openfpga_read_arch.cpp +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -1,23 +1,19 @@ +#ifndef OPENFPGA_READ_ARCH_TEMPLATE_H +#define OPENFPGA_READ_ARCH_TEMPLATE_H /******************************************************************** * This file includes functions to read an OpenFPGA architecture file * which are built on the libarchopenfpga library *******************************************************************/ -/* Headers from vtrutil library */ -#include "vtr_log.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from archopenfpga library */ #include "check_circuit_library.h" #include "check_tile_annotation.h" #include "circuit_library_utils.h" -#include "openfpga_read_arch.h" -#include "read_xml_openfpga_arch.h" -#include "write_xml_openfpga_arch.h" - -/* Include global variables of VPR */ +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" #include "globals.h" +#include "read_xml_openfpga_arch.h" +#include "vtr_log.h" +#include "write_xml_openfpga_arch.h" /* begin namespace openfpga */ namespace openfpga { @@ -29,8 +25,9 @@ namespace openfpga { * The command will accept an option '--file' which is the architecture * file provided by users *******************************************************************/ -int read_arch(OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context) { +template +int read_openfpga_arch_template(T& openfpga_context, const Command& cmd, + const CommandContext& cmd_context) { /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction @@ -77,8 +74,9 @@ int read_arch(OpenfpgaContext& openfpga_context, const Command& cmd, * The command will accept an option '--file' which is the architecture * file provided by users *******************************************************************/ -int write_arch(const OpenfpgaContext& openfpga_context, const Command& cmd, - const CommandContext& cmd_context) { +template +int write_openfpga_arch_template(const T& openfpga_context, const Command& cmd, + const CommandContext& cmd_context) { /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction @@ -103,9 +101,9 @@ int write_arch(const OpenfpgaContext& openfpga_context, const Command& cmd, * The command will accept an option '--file' which is the simulation setting * file provided by users *******************************************************************/ -int read_simulation_setting(OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context) { +template +int read_simulation_setting_template(T& openfpga_context, const Command& cmd, + const CommandContext& cmd_context) { /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction @@ -131,9 +129,10 @@ int read_simulation_setting(OpenfpgaContext& openfpga_context, * The command will accept an option '--file' which is the simulation setting * file provided by users *******************************************************************/ -int write_simulation_setting(const OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_simulation_setting_template(const T& openfpga_context, + const Command& cmd, + const CommandContext& cmd_context) { /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction @@ -160,9 +159,9 @@ int write_simulation_setting(const OpenfpgaContext& openfpga_context, * The command will accept an option '--file' which is the bitstream setting * file provided by users *******************************************************************/ -int read_bitstream_setting(OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context) { +template +int read_bitstream_setting_template(T& openfpga_context, const Command& cmd, + const CommandContext& cmd_context) { /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction @@ -188,9 +187,10 @@ int read_bitstream_setting(OpenfpgaContext& openfpga_context, * The command will accept an option '--file' which is the simulation setting * file provided by users *******************************************************************/ -int write_bitstream_setting(const OpenfpgaContext& openfpga_context, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_bitstream_setting_template(const T& openfpga_context, + const Command& cmd, + const CommandContext& cmd_context) { /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction @@ -210,3 +210,5 @@ int write_bitstream_setting(const OpenfpgaContext& openfpga_context, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_repack.h b/openfpga/src/base/openfpga_repack.h deleted file mode 100644 index 0ad9d5f73..000000000 --- a/openfpga/src/base/openfpga_repack.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef OPENFPGA_REPACK_H -#define OPENFPGA_REPACK_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int repack(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack_template.h similarity index 89% rename from openfpga/src/base/openfpga_repack.cpp rename to openfpga/src/base/openfpga_repack_template.h index 2d607b58c..42d552fef 100644 --- a/openfpga/src/base/openfpga_repack.cpp +++ b/openfpga/src/base/openfpga_repack_template.h @@ -1,22 +1,19 @@ +#ifndef OPENFPGA_REPACK_TEMPLATE_H +#define OPENFPGA_REPACK_TEMPLATE_H + /******************************************************************** * This file includes functions to compress the hierachy of routing architecture *******************************************************************/ -/* Headers from vtrutil library */ -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from librepackdc library */ #include "build_physical_truth_table.h" -#include "openfpga_repack.h" +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "globals.h" #include "read_xml_repack_design_constraints.h" #include "repack.h" #include "repack_design_constraints.h" - -/* Include global variables of VPR */ -#include "globals.h" +#include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { @@ -24,8 +21,9 @@ namespace openfpga { /******************************************************************** * A wrapper function to call the fabric_verilog function of FPGA-Verilog *******************************************************************/ -int repack(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int repack_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_design_constraints = cmd.option("design_constraints"); CommandOptionId opt_ignore_global_nets = cmd.option("ignore_global_nets_on_pins"); @@ -70,3 +68,5 @@ int repack(OpenfpgaContext& openfpga_ctx, const Command& cmd, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_sdc.h b/openfpga/src/base/openfpga_sdc.h deleted file mode 100644 index 8b039080c..000000000 --- a/openfpga/src/base/openfpga_sdc.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef OPENFPGA_SDC_H -#define OPENFPGA_SDC_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -int write_sdc_disable_timing_configure_ports( - const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp index ba1985a81..47e84c57e 100644 --- a/openfpga/src/base/openfpga_sdc_command.cpp +++ b/openfpga/src/base/openfpga_sdc_command.cpp @@ -6,301 +6,13 @@ *******************************************************************/ #include "openfpga_sdc_command.h" -#include "openfpga_sdc.h" +#include "openfpga_sdc_command_template.h" /* begin namespace openfpga */ namespace openfpga { -/******************************************************************** - * - Add a command to Shell environment: generate PnR SDC - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_pnr_sdc_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_pnr_sdc"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the output directory for SDC files"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--flatten_name' */ - shell_cmd.add_option("flatten_names", false, - "Use flatten names (no wildcards) in SDC files"); - - /* Add an option '--hierarchical' */ - shell_cmd.add_option( - "hierarchical", false, - "Output SDC files hierachically (without full path in hierarchy)"); - - /* Add an option '--output_hierarchy' */ - shell_cmd.add_option( - "output_hierarchy", false, - "Output hierachy of Multiple-Instance-Blocks (MIBs) to plain text file. " - "This is applied to constrain timing for grid, SBs and CBs"); - - /* Add an option '--time_unit' */ - CommandOptionId time_unit_opt = shell_cmd.add_option( - "time_unit", false, - "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s"); - shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); - - /* Add an option '--constrain_global_port' */ - shell_cmd.add_option("constrain_global_port", false, - "Constrain all the global ports of FPGA fabric"); - - /* Add an option '--constrain_non_clock_global_port' */ - shell_cmd.add_option( - "constrain_non_clock_global_port", false, - "Constrain all the non-clock global ports as clock ports of FPGA fabric"); - - /* Add an option '--constrain_grid' */ - shell_cmd.add_option("constrain_grid", false, - "Constrain all the grids of FPGA fabric"); - - /* Add an option '--constrain_sb' */ - shell_cmd.add_option("constrain_sb", false, - "Constrain all the switch blocks of FPGA fabric"); - - /* Add an option '--constrain_cb' */ - shell_cmd.add_option("constrain_cb", false, - "Constrain all the connection blocks of FPGA fabric"); - - /* Add an option '--constrain_configurable_memory_outputs' */ - shell_cmd.add_option( - "constrain_configurable_memory_outputs", false, - "Constrain all the outputs of configurable memories of FPGA fabric"); - - /* Add an option '--constrain_routing_multiplexer_outputs' */ - shell_cmd.add_option( - "constrain_routing_multiplexer_outputs", false, - "Constrain all the outputs of routing multiplexer of FPGA fabric"); - - /* Add an option '--constrain_switch_block_outputs' */ - shell_cmd.add_option( - "constrain_switch_block_outputs", false, - "Constrain all the outputs of switch blocks of FPGA fabric"); - - /* Add an option '--constrain_zero_delay_paths' */ - shell_cmd.add_option("constrain_zero_delay_paths", false, - "Constrain zero-delay paths in FPGA fabric"); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'write_fabric_verilog' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, - "generate SDC files to constrain the backend flow for FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, write_pnr_sdc); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: generate PnR SDC for configuration - *chain - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_configuration_chain_sdc_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_configuration_chain_sdc"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the SDC file to constrain configuration chain"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--time_unit' */ - CommandOptionId time_unit_opt = shell_cmd.add_option( - "time_unit", false, - "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s"); - shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); - - /* Add an option '--min_delay' */ - CommandOptionId min_dly_opt = shell_cmd.add_option( - "min_delay", false, "Specify the minimum delay to be used."); - shell_cmd.set_option_require_value(min_dly_opt, openfpga::OPT_STRING); - - /* Add an option '--max_delay' */ - CommandOptionId max_dly_opt = shell_cmd.add_option( - "max_delay", false, "Specify the maximum delay to be used."); - shell_cmd.set_option_require_value(max_dly_opt, openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add command 'write_configuration_chain_sdc' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, - "generate SDC files to constrain the configuration chain for FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, - write_configuration_chain_sdc); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: generate PnR SDC for configure ports - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId -add_openfpga_write_sdc_disable_timing_configure_ports_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_sdc_disable_timing_configure_ports"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = - shell_cmd.add_option("file", true, "Specify the output directory"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--flatten_name' */ - shell_cmd.add_option("flatten_names", false, - "Use flatten names (no wildcards) in SDC files"); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose outputs"); - - /* Add command 'write_configuration_chain_sdc' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, - "generate SDC files to disable timing for configure " - "ports across FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function( - shell_cmd_id, write_sdc_disable_timing_configure_ports); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: generate PnR SDC - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_analysis_sdc_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_analysis_sdc"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the output directory for SDC files"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add an option '--flatten_name' */ - shell_cmd.add_option("flatten_names", false, - "Use flatten names (no wildcards) in SDC files"); - - /* Add an option '--time_unit' */ - CommandOptionId time_unit_opt = shell_cmd.add_option( - "time_unit", false, - "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s"); - shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add command 'write_fabric_verilog' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, - "generate SDC files for timing analysis a PnRed FPGA " - "fabric mapped by a benchmark"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, write_analysis_sdc); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - void add_openfpga_sdc_commands(openfpga::Shell& shell) { - /* Get the unique id of 'build_fabric' command which is to be used in creating - * the dependency graph */ - const ShellCommandId& build_fabric_id = - shell.command(std::string("build_fabric")); - - /* Add a new class of commands */ - ShellCommandClassId openfpga_sdc_cmd_class = - shell.add_command_class("FPGA-SDC"); - - /******************************** - * Command 'write_pnr_sdc' - */ - /* The 'write_pnr_sdc' command should NOT be executed before 'build_fabric' */ - std::vector pnr_sdc_cmd_dependency; - pnr_sdc_cmd_dependency.push_back(build_fabric_id); - add_openfpga_write_pnr_sdc_command(shell, openfpga_sdc_cmd_class, - pnr_sdc_cmd_dependency); - - /******************************** - * Command 'write_configuration_chain_sdc' - */ - /* The 'write_configuration_chain_sdc' command should NOT be executed before - * 'build_fabric' */ - std::vector cc_sdc_cmd_dependency; - cc_sdc_cmd_dependency.push_back(build_fabric_id); - add_openfpga_write_configuration_chain_sdc_command( - shell, openfpga_sdc_cmd_class, cc_sdc_cmd_dependency); - - /******************************** - * Command 'write_sdc_disable_timing_configure_ports' - */ - /* The 'write_sdc_disable_timing_configure_ports' command should NOT be - * executed before 'build_fabric' */ - std::vector config_port_sdc_cmd_dependency; - config_port_sdc_cmd_dependency.push_back(build_fabric_id); - add_openfpga_write_sdc_disable_timing_configure_ports_command( - shell, openfpga_sdc_cmd_class, config_port_sdc_cmd_dependency); - - /******************************** - * Command 'write_analysis_sdc' - */ - /* The 'write_analysis_sdc' command should NOT be executed before - * 'build_fabric' */ - std::vector analysis_sdc_cmd_dependency; - analysis_sdc_cmd_dependency.push_back(build_fabric_id); - add_openfpga_write_analysis_sdc_command(shell, openfpga_sdc_cmd_class, - analysis_sdc_cmd_dependency); + add_openfpga_sdc_command_templates(shell); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_sdc_command_template.h b/openfpga/src/base/openfpga_sdc_command_template.h new file mode 100644 index 000000000..09c28cd5c --- /dev/null +++ b/openfpga/src/base/openfpga_sdc_command_template.h @@ -0,0 +1,315 @@ +#ifndef OPENFPGA_SDC_COMMAND_TEMPLATE_H +#define OPENFPGA_SDC_COMMAND_TEMPLATE_H +/******************************************************************** + * Add commands to the OpenFPGA shell interface, + * in purpose of generate SDC files + * - write_pnr_sdc : generate SDC to constrain the back-end flow for FPGA fabric + * - write_analysis_sdc: TODO: generate SDC based on users' implementations + *******************************************************************/ +#include "openfpga_sdc_template.h" +#include "shell.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * - Add a command to Shell environment: generate PnR SDC + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_pnr_sdc_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_pnr_sdc"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the output directory for SDC files"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--flatten_name' */ + shell_cmd.add_option("flatten_names", false, + "Use flatten names (no wildcards) in SDC files"); + + /* Add an option '--hierarchical' */ + shell_cmd.add_option( + "hierarchical", false, + "Output SDC files hierachically (without full path in hierarchy)"); + + /* Add an option '--output_hierarchy' */ + shell_cmd.add_option( + "output_hierarchy", false, + "Output hierachy of Multiple-Instance-Blocks (MIBs) to plain text file. " + "This is applied to constrain timing for grid, SBs and CBs"); + + /* Add an option '--time_unit' */ + CommandOptionId time_unit_opt = shell_cmd.add_option( + "time_unit", false, + "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s"); + shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); + + /* Add an option '--constrain_global_port' */ + shell_cmd.add_option("constrain_global_port", false, + "Constrain all the global ports of FPGA fabric"); + + /* Add an option '--constrain_non_clock_global_port' */ + shell_cmd.add_option( + "constrain_non_clock_global_port", false, + "Constrain all the non-clock global ports as clock ports of FPGA fabric"); + + /* Add an option '--constrain_grid' */ + shell_cmd.add_option("constrain_grid", false, + "Constrain all the grids of FPGA fabric"); + + /* Add an option '--constrain_sb' */ + shell_cmd.add_option("constrain_sb", false, + "Constrain all the switch blocks of FPGA fabric"); + + /* Add an option '--constrain_cb' */ + shell_cmd.add_option("constrain_cb", false, + "Constrain all the connection blocks of FPGA fabric"); + + /* Add an option '--constrain_configurable_memory_outputs' */ + shell_cmd.add_option( + "constrain_configurable_memory_outputs", false, + "Constrain all the outputs of configurable memories of FPGA fabric"); + + /* Add an option '--constrain_routing_multiplexer_outputs' */ + shell_cmd.add_option( + "constrain_routing_multiplexer_outputs", false, + "Constrain all the outputs of routing multiplexer of FPGA fabric"); + + /* Add an option '--constrain_switch_block_outputs' */ + shell_cmd.add_option( + "constrain_switch_block_outputs", false, + "Constrain all the outputs of switch blocks of FPGA fabric"); + + /* Add an option '--constrain_zero_delay_paths' */ + shell_cmd.add_option("constrain_zero_delay_paths", false, + "Constrain zero-delay paths in FPGA fabric"); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'write_fabric_verilog' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, + "generate SDC files to constrain the backend flow for FPGA fabric", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, + write_pnr_sdc_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: generate PnR SDC for configuration + *chain + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_configuration_chain_sdc_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_configuration_chain_sdc"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the SDC file to constrain configuration chain"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--time_unit' */ + CommandOptionId time_unit_opt = shell_cmd.add_option( + "time_unit", false, + "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s"); + shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); + + /* Add an option '--min_delay' */ + CommandOptionId min_dly_opt = shell_cmd.add_option( + "min_delay", false, "Specify the minimum delay to be used."); + shell_cmd.set_option_require_value(min_dly_opt, openfpga::OPT_STRING); + + /* Add an option '--max_delay' */ + CommandOptionId max_dly_opt = shell_cmd.add_option( + "max_delay", false, "Specify the maximum delay to be used."); + shell_cmd.set_option_require_value(max_dly_opt, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add command 'write_configuration_chain_sdc' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, + "generate SDC files to constrain the configuration chain for FPGA fabric", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function( + shell_cmd_id, write_configuration_chain_sdc_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: generate PnR SDC for configure ports + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_sdc_disable_timing_configure_ports_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_sdc_disable_timing_configure_ports"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = + shell_cmd.add_option("file", true, "Specify the output directory"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--flatten_name' */ + shell_cmd.add_option("flatten_names", false, + "Use flatten names (no wildcards) in SDC files"); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose outputs"); + + /* Add command 'write_configuration_chain_sdc' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "generate SDC files to disable timing for configure " + "ports across FPGA fabric", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function( + shell_cmd_id, write_sdc_disable_timing_configure_ports_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: generate PnR SDC + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_analysis_sdc_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_analysis_sdc"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the output directory for SDC files"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add an option '--flatten_name' */ + shell_cmd.add_option("flatten_names", false, + "Use flatten names (no wildcards) in SDC files"); + + /* Add an option '--time_unit' */ + CommandOptionId time_unit_opt = shell_cmd.add_option( + "time_unit", false, + "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s"); + shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add command 'write_fabric_verilog' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "generate SDC files for timing analysis a PnRed FPGA " + "fabric mapped by a benchmark", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, + write_analysis_sdc_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +template +void add_openfpga_sdc_command_templates(openfpga::Shell& shell, + const bool& hidden = false) { + /* Get the unique id of 'build_fabric' command which is to be used in creating + * the dependency graph */ + const ShellCommandId& build_fabric_id = + shell.command(std::string("build_fabric")); + + /* Add a new class of commands */ + ShellCommandClassId openfpga_sdc_cmd_class = + shell.add_command_class("FPGA-SDC"); + + /******************************** + * Command 'write_pnr_sdc' + */ + /* The 'write_pnr_sdc' command should NOT be executed before 'build_fabric' */ + std::vector pnr_sdc_cmd_dependency; + pnr_sdc_cmd_dependency.push_back(build_fabric_id); + add_write_pnr_sdc_command_template(shell, openfpga_sdc_cmd_class, + pnr_sdc_cmd_dependency, hidden); + + /******************************** + * Command 'write_configuration_chain_sdc' + */ + /* The 'write_configuration_chain_sdc' command should NOT be executed before + * 'build_fabric' */ + std::vector cc_sdc_cmd_dependency; + cc_sdc_cmd_dependency.push_back(build_fabric_id); + add_write_configuration_chain_sdc_command_template( + shell, openfpga_sdc_cmd_class, cc_sdc_cmd_dependency, hidden); + + /******************************** + * Command 'write_sdc_disable_timing_configure_ports' + */ + /* The 'write_sdc_disable_timing_configure_ports' command should NOT be + * executed before 'build_fabric' */ + std::vector config_port_sdc_cmd_dependency; + config_port_sdc_cmd_dependency.push_back(build_fabric_id); + add_write_sdc_disable_timing_configure_ports_command_template( + shell, openfpga_sdc_cmd_class, config_port_sdc_cmd_dependency, hidden); + + /******************************** + * Command 'write_analysis_sdc' + */ + /* The 'write_analysis_sdc' command should NOT be executed before + * 'build_fabric' */ + std::vector analysis_sdc_cmd_dependency; + analysis_sdc_cmd_dependency.push_back(build_fabric_id); + add_write_analysis_sdc_command_template( + shell, openfpga_sdc_cmd_class, analysis_sdc_cmd_dependency, hidden); +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc_template.h similarity index 92% rename from openfpga/src/base/openfpga_sdc.cpp rename to openfpga/src/base/openfpga_sdc_template.h index c99275ad5..fe3a25be6 100644 --- a/openfpga/src/base/openfpga_sdc.cpp +++ b/openfpga/src/base/openfpga_sdc_template.h @@ -1,25 +1,21 @@ +#ifndef OPENFPGA_SDC_TEMPLATE_H +#define OPENFPGA_SDC_TEMPLATE_H /******************************************************************** * This file includes functions to compress the hierachy of routing architecture *******************************************************************/ -/* Headers from vtrutil library */ -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from openfpgautil library */ #include "analysis_sdc_writer.h" #include "circuit_library_utils.h" +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" #include "configuration_chain_sdc_writer.h" #include "configure_port_sdc_writer.h" +#include "globals.h" #include "openfpga_digest.h" #include "openfpga_scale.h" -#include "openfpga_sdc.h" #include "pnr_sdc_writer.h" - -/* Include global variables of VPR */ -#include "globals.h" +#include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { @@ -27,8 +23,9 @@ namespace openfpga { /******************************************************************** * A wrapper function to call the PnR SDC generator of FPGA-SDC *******************************************************************/ -int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int write_pnr_sdc_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_flatten_names = cmd.option("flatten_names"); CommandOptionId opt_hierarchical = cmd.option("hierarchical"); @@ -115,9 +112,10 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx, const Command& cmd, * A wrapper function to call the PnR SDC generator on configuration chain * of FPGA-SDC *******************************************************************/ -int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_configuration_chain_sdc_template(const T& openfpga_ctx, + const Command& cmd, + const CommandContext& cmd_context) { /* If the configuration protocol is not a configuration chain, we will not * write anything */ if (CONFIG_MEM_SCAN_CHAIN != openfpga_ctx.arch().config_protocol.type()) { @@ -157,8 +155,9 @@ int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx, * A wrapper function to call the PnR SDC generator on routing multiplexers * of FPGA-SDC *******************************************************************/ -int write_sdc_disable_timing_configure_ports( - const OpenfpgaContext& openfpga_ctx, const Command& cmd, +template +int write_sdc_disable_timing_configure_ports_template( + const T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { /* Get command options */ CommandOptionId opt_output_dir = cmd.option("file"); @@ -187,8 +186,9 @@ int write_sdc_disable_timing_configure_ports( /******************************************************************** * A wrapper function to call the analysis SDC generator of FPGA-SDC *******************************************************************/ -int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int write_analysis_sdc_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_flatten_names = cmd.option("flatten_names"); CommandOptionId opt_time_unit = cmd.option("time_unit"); @@ -226,3 +226,5 @@ int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx, const Command& cmd, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index 08e9c7497..d9f055041 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -5,699 +5,13 @@ *******************************************************************/ #include "openfpga_setup_command.h" -#include "check_netlist_naming_conflict.h" -#include "openfpga_build_fabric.h" -#include "openfpga_link_arch.h" -#include "openfpga_lut_truth_table_fixup.h" -#include "openfpga_pb_pin_fixup.h" -#include "openfpga_pcf2place.h" -#include "openfpga_read_arch.h" -#include "openfpga_write_gsb.h" +#include "openfpga_setup_command_template.h" /* begin namespace openfpga */ namespace openfpga { -/******************************************************************** - * - Add a command to Shell environment: read_openfpga_arch - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_read_arch_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id) { - Command shell_cmd("read_openfpga_arch"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_arch_file = - shell_cmd.add_option("file", true, "file path to the architecture XML"); - shell_cmd.set_option_short_name(opt_arch_file, "f"); - shell_cmd.set_option_require_value(opt_arch_file, openfpga::OPT_STRING); - - /* Add command 'read_openfpga_arch' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "read OpenFPGA architecture file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, read_arch); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_openfpga_arch - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_arch_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_openfpga_arch"); - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = - shell_cmd.add_option("file", true, "file path to the architecture XML"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add command 'write_openfpga_arch' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "write OpenFPGA architecture file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, write_arch); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: read_openfpga_simulation_setting - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_read_simulation_setting_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id) { - Command shell_cmd("read_openfpga_simulation_setting"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "file path to the simulation setting XML"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add command 'read_openfpga_arch' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "read OpenFPGA simulation setting file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, read_simulation_setting); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_openfpga_simulation_setting - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_simulation_setting_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_openfpga_simulation_setting"); - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "file path to the simulation setting XML"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add command 'write_openfpga_arch' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "write OpenFPGA simulation setting file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, - write_simulation_setting); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: read_openfpga_bitstream_setting - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_read_bitstream_setting_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id) { - Command shell_cmd("read_openfpga_bitstream_setting"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "file path to the bitstream setting XML"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add command 'read_openfpga_bitstream_setting' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "read OpenFPGA bitstream setting file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, read_bitstream_setting); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_openfpga_bitstream_setting - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_bitstream_setting_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_openfpga_bitstream_setting"); - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "file path to the bitstream setting XML"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add command 'write_openfpga_bitstream_setting' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "write OpenFPGA bitstream setting file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, - write_bitstream_setting); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: link_openfpga_arch - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_link_arch_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("link_openfpga_arch"); - - /* Add an option '--activity_file'*/ - CommandOptionId opt_act_file = shell_cmd.add_option( - "activity_file", false, "file path to the signal activity"); - shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING); - - /* Add an option '--sort_gsb_chan_node_in_edges'*/ - shell_cmd.add_option("sort_gsb_chan_node_in_edges", false, - "Sort all the incoming edges for each routing track " - "output node in General Switch Blocks (GSBs)"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Show verbose outputs"); - - /* Add command 'link_openfpga_arch' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "Bind OpenFPGA architecture to VPR"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, link_arch); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_gsb_to_xml - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_gsb_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_gsb_to_xml"); - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "path to the directory that stores the XML files"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add an option '--unique' */ - shell_cmd.add_option("unique", false, "Only output unique GSB blocks"); - - /* Add an option '--exclude_rr_info' */ - shell_cmd.add_option("exclude_rr_info", false, - "Exclude routing resource graph information from output " - "files, e.g., node id as well as other attributes. This " - "is useful to check the connection inside GSBs purely."); - - /* Add an option '--exclude'*/ - CommandOptionId opt_exclude = - shell_cmd.add_option("exclude", false, - "Exclude part of the GSB data to be outputted. Can be " - "[``sb``|``cbx``|``cby``]. Users can exclude multiple " - "parts by using a splitter ``,``"); - shell_cmd.set_option_require_value(opt_exclude, openfpga::OPT_STRING); - - /* Add an option '--gsb_names'*/ - CommandOptionId opt_gsb_names = - shell_cmd.add_option("gsb_names", false, - "Specify the name of GSB to be outputted. Users can " - "specify multiple GSBs by using a splitter ``,``"); - shell_cmd.set_option_require_value(opt_gsb_names, openfpga::OPT_STRING); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Show verbose outputs"); - - /* Add command 'write_openfpga_arch' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, - "write internal structures of General Switch Blocks to XML file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, write_gsb); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: check_netlist_naming_conflict - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_check_netlist_naming_conflict_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("check_netlist_naming_conflict"); - - /* Add an option '--fix' */ - shell_cmd.add_option("fix", false, "Apply correction to any conflicts found"); - - /* Add an option '--report' */ - CommandOptionId opt_rpt = shell_cmd.add_option( - "report", false, "Output a report file about what any correction applied"); - shell_cmd.set_option_require_value(opt_rpt, openfpga::OPT_STRING); - - /* Add command 'check_netlist_naming_conflict' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, - "Check any block/net naming in users' BLIF netlist " - "violates the syntax of fabric generator"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, - check_netlist_naming_conflict); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: pb_pin_fixup - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_pb_pin_fixup_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("pb_pin_fixup"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Show verbose outputs"); - - /* Add command 'pb_pin_fixup' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, - "Fix up the packing results due to pin swapping during routing stage"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, pb_pin_fixup); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: lut_truth_table_fixup - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_lut_truth_table_fixup_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("lut_truth_table_fixup"); - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Show verbose outputs"); - - /* Add command 'lut_truth_table_fixup' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, - "Fix up the truth table of Look-Up Tables due to pin " - "swapping during packing stage"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, lut_truth_table_fixup); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: build_fabric - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_build_fabric_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("build_fabric"); - - /* Add an option '--frame_view' */ - shell_cmd.add_option( - "frame_view", false, - "Build only frame view of the fabric (nets are skipped)"); - - /* Add an option '--compress_routing' */ - shell_cmd.add_option("compress_routing", false, - "Compress the number of unique routing modules by " - "identifying the unique GSBs"); - - /* Add an option '--duplicate_grid_pin' */ - shell_cmd.add_option("duplicate_grid_pin", false, - "Duplicate the pins on the same side of a grid"); - - /* Add an option '--load_fabric_key' */ - CommandOptionId opt_load_fkey = shell_cmd.add_option( - "load_fabric_key", false, "load the fabric key from the given file"); - shell_cmd.set_option_require_value(opt_load_fkey, openfpga::OPT_STRING); - - /* Add an option '--write_fabric_key' */ - CommandOptionId opt_write_fkey = shell_cmd.add_option( - "write_fabric_key", false, "output current fabric key to a file"); - shell_cmd.set_option_require_value(opt_write_fkey, openfpga::OPT_STRING); - - /* Add an option '--generate_random_fabric_key' */ - shell_cmd.add_option("generate_random_fabric_key", false, - "Create a random fabric key which will shuffle the " - "memory address for encryption purpose"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Show verbose outputs"); - - /* Add command 'compact_routing_hierarchy' to the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "Build the FPGA fabric in a graph of modules"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, build_fabric); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_fabric_hierarchy - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_fabric_hierarchy_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_fabric_hierarchy"); - - /* Add an option '--file' */ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "Specify the file name to write the hierarchy to"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add an option '--depth' */ - CommandOptionId opt_depth = shell_cmd.add_option( - "depth", false, - "Specify the depth of hierarchy to which the writer should stop"); - shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_INT); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Show verbose outputs"); - - /* Add command 'write_fabric_hierarchy' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "Write the hierarchy of FPGA fabric graph to a plain-text file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function(shell_cmd_id, - write_fabric_hierarchy); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write_fabric_io_info - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_fabric_io_info_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_fabric_io_info"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, "file path to output the I/O information"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command the Shell */ - ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, - "Write the I/O information, e.g., locations and similar " - "attributes, to a file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_fabric_io_info); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: pcf2place - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_pcf2place_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id) { - Command shell_cmd("pcf2place"); - - /* Add an option '--pcf'*/ - CommandOptionId opt_pcf_file = - shell_cmd.add_option("pcf", true, "file path to the user pin constraint"); - shell_cmd.set_option_require_value(opt_pcf_file, openfpga::OPT_STRING); - - /* Add an option '--blif'*/ - CommandOptionId opt_blif_file = shell_cmd.add_option( - "blif", true, "file path to the synthesized netlist (.blif)"); - shell_cmd.set_option_require_value(opt_blif_file, openfpga::OPT_STRING); - - /* Add an option '--fpga_io_map'*/ - CommandOptionId opt_fpga_io_map_file = shell_cmd.add_option( - "fpga_io_map", true, "file path to FPGA I/O location map (.xml)"); - shell_cmd.set_option_require_value(opt_fpga_io_map_file, - openfpga::OPT_STRING); - - /* Add an option '--pin_table'*/ - CommandOptionId opt_pin_table_file = shell_cmd.add_option( - "pin_table", true, "file path to the pin table (.csv)"); - shell_cmd.set_option_require_value(opt_pin_table_file, openfpga::OPT_STRING); - - /* Add an option '--fpga_fix_pins'*/ - CommandOptionId opt_fpga_fix_pins_file = shell_cmd.add_option( - "fpga_fix_pins", true, - "file path to the output fix-pin placement file (.place)"); - shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, - openfpga::OPT_STRING); - - /* Add an option '--pin_table_direction_convention'*/ - CommandOptionId opt_pin_table_dir_convention = - shell_cmd.add_option("pin_table_direction_convention", false, - "the convention to follow when inferring pin " - "direction from the name of ports in pin table file"); - shell_cmd.set_option_require_value(opt_pin_table_dir_convention, - openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "Convert user Pin Constraint File (.pcf) to an placement file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, pcf2place_wrapper); - - return shell_cmd_id; -} - void add_openfpga_setup_commands(openfpga::Shell& shell) { - /* Get the unique id of 'vpr' command which is to be used in creating the - * dependency graph */ - const ShellCommandId& vpr_cmd_id = shell.command(std::string("vpr")); - - /* Add a new class of commands */ - ShellCommandClassId openfpga_setup_cmd_class = - shell.add_command_class("OpenFPGA setup"); - - /******************************** - * Command 'pcf2place' - */ - add_openfpga_pcf2place_command(shell, openfpga_setup_cmd_class); - - /******************************** - * Command 'read_openfpga_arch' - */ - ShellCommandId read_arch_cmd_id = - add_openfpga_read_arch_command(shell, openfpga_setup_cmd_class); - - /******************************** - * Command 'write_openfpga_arch' - */ - /* The 'write_openfpga_arch' command should NOT be executed before - * 'read_openfpga_arch' */ - std::vector write_arch_dependent_cmds(1, read_arch_cmd_id); - add_openfpga_write_arch_command(shell, openfpga_setup_cmd_class, - write_arch_dependent_cmds); - - /******************************** - * Command 'read_openfpga_simulation_setting' - */ - ShellCommandId read_sim_setting_cmd_id = - add_openfpga_read_simulation_setting_command(shell, - openfpga_setup_cmd_class); - - /******************************** - * Command 'write_openfpga_simulation_setting' - */ - /* The 'write_openfpga_simulation_setting' command should NOT be executed - * before 'read_openfpga_simulation_setting' */ - std::vector write_sim_setting_dependent_cmds( - 1, read_sim_setting_cmd_id); - add_openfpga_write_simulation_setting_command( - shell, openfpga_setup_cmd_class, write_sim_setting_dependent_cmds); - - /******************************** - * Command 'read_openfpga_bitstream_setting' - */ - ShellCommandId read_bitstream_setting_cmd_id = - add_openfpga_read_bitstream_setting_command(shell, - openfpga_setup_cmd_class); - - /******************************** - * Command 'write_openfpga_bitstream_setting' - */ - /* The 'write_openfpga_bitstream_setting' command should NOT be executed - * before 'read_openfpga_bitstream_setting' */ - std::vector write_bitstream_setting_dependent_cmds( - 1, read_bitstream_setting_cmd_id); - add_openfpga_write_bitstream_setting_command( - shell, openfpga_setup_cmd_class, write_bitstream_setting_dependent_cmds); - - /******************************** - * Command 'link_openfpga_arch' - */ - /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */ - std::vector link_arch_dependent_cmds; - link_arch_dependent_cmds.push_back(read_arch_cmd_id); - /* TODO: This will be uncommented when openfpga flow script is updated - */ - link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id); - link_arch_dependent_cmds.push_back(vpr_cmd_id); - ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command( - shell, openfpga_setup_cmd_class, link_arch_dependent_cmds); - - /******************************** - * Command 'write_gsb' - */ - /* The 'write_gsb' command should NOT be executed before 'link_openfpga_arch' - */ - std::vector write_gsb_dependent_cmds; - write_gsb_dependent_cmds.push_back(link_arch_cmd_id); - add_openfpga_write_gsb_command(shell, openfpga_setup_cmd_class, - write_gsb_dependent_cmds); - - /******************************************* - * Command 'check_netlist_naming_conflict' - */ - /* The 'check_netlist_naming_conflict' command should NOT be executed before - * 'vpr' */ - std::vector nlist_naming_dependent_cmds; - nlist_naming_dependent_cmds.push_back(vpr_cmd_id); - add_openfpga_check_netlist_naming_conflict_command( - shell, openfpga_setup_cmd_class, nlist_naming_dependent_cmds); - - /******************************** - * Command 'pb_pin_fixup' - */ - /* The 'pb_pin_fixup' command should NOT be executed before - * 'read_openfpga_arch' and 'vpr' */ - std::vector pb_pin_fixup_dependent_cmds; - pb_pin_fixup_dependent_cmds.push_back(read_arch_cmd_id); - pb_pin_fixup_dependent_cmds.push_back(vpr_cmd_id); - add_openfpga_pb_pin_fixup_command(shell, openfpga_setup_cmd_class, - pb_pin_fixup_dependent_cmds); - - /******************************** - * Command 'lut_truth_table_fixup' - */ - /* The 'lut_truth_table_fixup' command should NOT be executed before - * 'read_openfpga_arch' and 'vpr' */ - std::vector lut_tt_fixup_dependent_cmds; - lut_tt_fixup_dependent_cmds.push_back(read_arch_cmd_id); - lut_tt_fixup_dependent_cmds.push_back(vpr_cmd_id); - add_openfpga_lut_truth_table_fixup_command(shell, openfpga_setup_cmd_class, - lut_tt_fixup_dependent_cmds); - /******************************** - * Command 'build_fabric' - */ - /* The 'build_fabric' command should NOT be executed before - * 'link_openfpga_arch' */ - std::vector build_fabric_dependent_cmds; - build_fabric_dependent_cmds.push_back(link_arch_cmd_id); - ShellCommandId build_fabric_cmd_id = add_openfpga_build_fabric_command( - shell, openfpga_setup_cmd_class, build_fabric_dependent_cmds); - - /******************************** - * Command 'write_fabric_hierarchy' - */ - /* The 'write_fabric_hierarchy' command should NOT be executed before - * 'build_fabric' */ - std::vector write_fabric_hie_dependent_cmds; - write_fabric_hie_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_fabric_hierarchy_command(shell, openfpga_setup_cmd_class, - write_fabric_hie_dependent_cmds); - - /******************************** - * Command 'write_fabric_io_info' - */ - /* The 'write_fabric_io_info' command should NOT be executed before - * 'build_fabric' */ - std::vector cmd_dependency_write_fabric_io_info; - cmd_dependency_write_fabric_io_info.push_back(build_fabric_cmd_id); - add_openfpga_write_fabric_io_info_command( - shell, openfpga_setup_cmd_class, cmd_dependency_write_fabric_io_info); + add_setup_command_templates(shell); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h new file mode 100644 index 000000000..d7ad1a654 --- /dev/null +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -0,0 +1,727 @@ +#ifndef OPENFPGA_SETUP_COMMAND_TEMPLATE_H +#define OPENFPGA_SETUP_COMMAND_TEMPLATE_H +/******************************************************************** + * Add commands to the OpenFPGA shell interface, + * in purpose of setting up OpenFPGA core engine, including: + * - read_openfpga_arch : read OpenFPGA architecture file + *******************************************************************/ +#include "check_netlist_naming_conflict_template.h" +#include "openfpga_build_fabric_template.h" +#include "openfpga_link_arch_template.h" +#include "openfpga_lut_truth_table_fixup_template.h" +#include "openfpga_pb_pin_fixup_template.h" +#include "openfpga_pcf2place_template.h" +#include "openfpga_read_arch_template.h" +#include "openfpga_write_gsb_template.h" +#include "shell.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * - Add a command to Shell environment: read_openfpga_arch + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_read_openfpga_arch_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const bool& hidden) { + Command shell_cmd("read_openfpga_arch"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_arch_file = + shell_cmd.add_option("file", true, "file path to the architecture XML"); + shell_cmd.set_option_short_name(opt_arch_file, "f"); + shell_cmd.set_option_require_value(opt_arch_file, openfpga::OPT_STRING); + + /* Add command 'read_openfpga_arch' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "read OpenFPGA architecture file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + read_openfpga_arch_template); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_openfpga_arch + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_openfpga_arch_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_openfpga_arch"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = + shell_cmd.add_option("file", true, "file path to the architecture XML"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add command 'write_openfpga_arch' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "write OpenFPGA architecture file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, + write_openfpga_arch_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: read_openfpga_simulation_setting + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_read_simulation_setting_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const bool& hidden) { + Command shell_cmd("read_openfpga_simulation_setting"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "file path to the simulation setting XML"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add command 'read_openfpga_arch' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "read OpenFPGA simulation setting file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + read_simulation_setting_template); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_openfpga_simulation_setting + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_simulation_setting_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_openfpga_simulation_setting"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "file path to the simulation setting XML"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add command 'write_openfpga_arch' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "write OpenFPGA simulation setting file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function( + shell_cmd_id, write_simulation_setting_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: read_openfpga_bitstream_setting + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_read_bitstream_setting_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const bool& hidden) { + Command shell_cmd("read_openfpga_bitstream_setting"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "file path to the bitstream setting XML"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add command 'read_openfpga_bitstream_setting' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "read OpenFPGA bitstream setting file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + read_bitstream_setting_template); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_openfpga_bitstream_setting + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_bitstream_setting_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_openfpga_bitstream_setting"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "file path to the bitstream setting XML"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add command 'write_openfpga_bitstream_setting' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "write OpenFPGA bitstream setting file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, + write_bitstream_setting_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: link_openfpga_arch + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_link_arch_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("link_openfpga_arch"); + + /* Add an option '--activity_file'*/ + CommandOptionId opt_act_file = shell_cmd.add_option( + "activity_file", false, "file path to the signal activity"); + shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING); + + /* Add an option '--sort_gsb_chan_node_in_edges'*/ + shell_cmd.add_option("sort_gsb_chan_node_in_edges", false, + "Sort all the incoming edges for each routing track " + "output node in General Switch Blocks (GSBs)"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'link_openfpga_arch' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "Bind OpenFPGA architecture to VPR", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, link_arch_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_gsb_to_xml + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_gsb_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_gsb_to_xml"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "path to the directory that stores the XML files"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--unique' */ + shell_cmd.add_option("unique", false, "Only output unique GSB blocks"); + + /* Add an option '--exclude_rr_info' */ + shell_cmd.add_option("exclude_rr_info", false, + "Exclude routing resource graph information from output " + "files, e.g., node id as well as other attributes. This " + "is useful to check the connection inside GSBs purely."); + + /* Add an option '--exclude'*/ + CommandOptionId opt_exclude = + shell_cmd.add_option("exclude", false, + "Exclude part of the GSB data to be outputted. Can be " + "[``sb``|``cbx``|``cby``]. Users can exclude multiple " + "parts by using a splitter ``,``"); + shell_cmd.set_option_require_value(opt_exclude, openfpga::OPT_STRING); + + /* Add an option '--gsb_names'*/ + CommandOptionId opt_gsb_names = + shell_cmd.add_option("gsb_names", false, + "Specify the name of GSB to be outputted. Users can " + "specify multiple GSBs by using a splitter ``,``"); + shell_cmd.set_option_require_value(opt_gsb_names, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'write_openfpga_arch' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "write internal structures of General Switch Blocks to XML file", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, write_gsb_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: check_netlist_naming_conflict + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_check_netlist_naming_conflict_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("check_netlist_naming_conflict"); + + /* Add an option '--fix' */ + shell_cmd.add_option("fix", false, "Apply correction to any conflicts found"); + + /* Add an option '--report' */ + CommandOptionId opt_rpt = shell_cmd.add_option( + "report", false, "Output a report file about what any correction applied"); + shell_cmd.set_option_require_value(opt_rpt, openfpga::OPT_STRING); + + /* Add command 'check_netlist_naming_conflict' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "Check any block/net naming in users' BLIF netlist " + "violates the syntax of fabric generator", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + check_netlist_naming_conflict_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: pb_pin_fixup + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_pb_pin_fixup_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("pb_pin_fixup"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'pb_pin_fixup' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, + "Fix up the packing results due to pin swapping during routing stage", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, pb_pin_fixup_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: lut_truth_table_fixup + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_lut_truth_table_fixup_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("lut_truth_table_fixup"); + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'lut_truth_table_fixup' to the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "Fix up the truth table of Look-Up Tables due to pin " + "swapping during packing stage", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + lut_truth_table_fixup_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: build_fabric + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_build_fabric_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("build_fabric"); + + /* Add an option '--frame_view' */ + shell_cmd.add_option( + "frame_view", false, + "Build only frame view of the fabric (nets are skipped)"); + + /* Add an option '--compress_routing' */ + shell_cmd.add_option("compress_routing", false, + "Compress the number of unique routing modules by " + "identifying the unique GSBs"); + + /* Add an option '--duplicate_grid_pin' */ + shell_cmd.add_option("duplicate_grid_pin", false, + "Duplicate the pins on the same side of a grid"); + + /* Add an option '--load_fabric_key' */ + CommandOptionId opt_load_fkey = shell_cmd.add_option( + "load_fabric_key", false, "load the fabric key from the given file"); + shell_cmd.set_option_require_value(opt_load_fkey, openfpga::OPT_STRING); + + /* Add an option '--write_fabric_key' */ + CommandOptionId opt_write_fkey = shell_cmd.add_option( + "write_fabric_key", false, "output current fabric key to a file"); + shell_cmd.set_option_require_value(opt_write_fkey, openfpga::OPT_STRING); + + /* Add an option '--generate_random_fabric_key' */ + shell_cmd.add_option("generate_random_fabric_key", false, + "Create a random fabric key which will shuffle the " + "memory address for encryption purpose"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'compact_routing_hierarchy' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Build the FPGA fabric in a graph of modules", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, build_fabric_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_fabric_hierarchy + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_hierarchy_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_fabric_hierarchy"); + + /* Add an option '--file' */ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "Specify the file name to write the hierarchy to"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--depth' */ + CommandOptionId opt_depth = shell_cmd.add_option( + "depth", false, + "Specify the depth of hierarchy to which the writer should stop"); + shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_INT); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'write_fabric_hierarchy' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Write the hierarchy of FPGA fabric graph to a plain-text file", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function(shell_cmd_id, + write_fabric_hierarchy_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write_fabric_io_info + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_io_info_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_fabric_io_info"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "file path to output the I/O information"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command the Shell */ + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "Write the I/O information, e.g., locations and similar " + "attributes, to a file", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_fabric_io_info_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: pcf2place + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_pcf2place_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const bool& hidden) { + Command shell_cmd("pcf2place"); + + /* Add an option '--pcf'*/ + CommandOptionId opt_pcf_file = + shell_cmd.add_option("pcf", true, "file path to the user pin constraint"); + shell_cmd.set_option_require_value(opt_pcf_file, openfpga::OPT_STRING); + + /* Add an option '--blif'*/ + CommandOptionId opt_blif_file = shell_cmd.add_option( + "blif", true, "file path to the synthesized netlist (.blif)"); + shell_cmd.set_option_require_value(opt_blif_file, openfpga::OPT_STRING); + + /* Add an option '--fpga_io_map'*/ + CommandOptionId opt_fpga_io_map_file = shell_cmd.add_option( + "fpga_io_map", true, "file path to FPGA I/O location map (.xml)"); + shell_cmd.set_option_require_value(opt_fpga_io_map_file, + openfpga::OPT_STRING); + + /* Add an option '--pin_table'*/ + CommandOptionId opt_pin_table_file = shell_cmd.add_option( + "pin_table", true, "file path to the pin table (.csv)"); + shell_cmd.set_option_require_value(opt_pin_table_file, openfpga::OPT_STRING); + + /* Add an option '--fpga_fix_pins'*/ + CommandOptionId opt_fpga_fix_pins_file = shell_cmd.add_option( + "fpga_fix_pins", true, + "file path to the output fix-pin placement file (.place)"); + shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, + openfpga::OPT_STRING); + + /* Add an option '--pin_table_direction_convention'*/ + CommandOptionId opt_pin_table_dir_convention = + shell_cmd.add_option("pin_table_direction_convention", false, + "the convention to follow when inferring pin " + "direction from the name of ports in pin table file"); + shell_cmd.set_option_require_value(opt_pin_table_dir_convention, + openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Convert user Pin Constraint File (.pcf) to an placement file", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + pcf2place_wrapper_template); + + return shell_cmd_id; +} + +template +void add_setup_command_templates(openfpga::Shell& shell, + const bool& hidden = false) { + /* Get the unique id of 'vpr' command which is to be used in creating the + * dependency graph */ + const ShellCommandId& vpr_cmd_id = shell.command(std::string("vpr")); + + /* Add a new class of commands */ + ShellCommandClassId openfpga_setup_cmd_class = + shell.add_command_class("OpenFPGA setup"); + + /******************************** + * Command 'pcf2place' + */ + add_pcf2place_command_template(shell, openfpga_setup_cmd_class, hidden); + + /******************************** + * Command 'read_openfpga_arch' + */ + ShellCommandId read_arch_cmd_id = add_read_openfpga_arch_command_template( + shell, openfpga_setup_cmd_class, hidden); + + /******************************** + * Command 'write_openfpga_arch' + */ + /* The 'write_openfpga_arch' command should NOT be executed before + * 'read_openfpga_arch' */ + std::vector write_arch_dependent_cmds(1, read_arch_cmd_id); + add_write_openfpga_arch_command_template( + shell, openfpga_setup_cmd_class, write_arch_dependent_cmds, hidden); + + /******************************** + * Command 'read_openfpga_simulation_setting' + */ + ShellCommandId read_sim_setting_cmd_id = + add_read_simulation_setting_command_template( + shell, openfpga_setup_cmd_class, hidden); + + /******************************** + * Command 'write_openfpga_simulation_setting' + */ + /* The 'write_openfpga_simulation_setting' command should NOT be executed + * before 'read_openfpga_simulation_setting' */ + std::vector write_sim_setting_dependent_cmds( + 1, read_sim_setting_cmd_id); + add_write_simulation_setting_command_template( + shell, openfpga_setup_cmd_class, write_sim_setting_dependent_cmds, hidden); + + /******************************** + * Command 'read_openfpga_bitstream_setting' + */ + ShellCommandId read_bitstream_setting_cmd_id = + add_read_bitstream_setting_command_template( + shell, openfpga_setup_cmd_class, hidden); + + /******************************** + * Command 'write_openfpga_bitstream_setting' + */ + /* The 'write_openfpga_bitstream_setting' command should NOT be executed + * before 'read_openfpga_bitstream_setting' */ + std::vector write_bitstream_setting_dependent_cmds( + 1, read_bitstream_setting_cmd_id); + add_write_bitstream_setting_command_template( + shell, openfpga_setup_cmd_class, write_bitstream_setting_dependent_cmds, + hidden); + + /******************************** + * Command 'link_openfpga_arch' + */ + /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */ + std::vector link_arch_dependent_cmds; + link_arch_dependent_cmds.push_back(read_arch_cmd_id); + /* TODO: This will be uncommented when openfpga flow script is updated + */ + link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id); + link_arch_dependent_cmds.push_back(vpr_cmd_id); + ShellCommandId link_arch_cmd_id = add_link_arch_command_template( + shell, openfpga_setup_cmd_class, link_arch_dependent_cmds, hidden); + + /******************************** + * Command 'write_gsb' + */ + /* The 'write_gsb' command should NOT be executed before 'link_openfpga_arch' + */ + std::vector write_gsb_dependent_cmds; + write_gsb_dependent_cmds.push_back(link_arch_cmd_id); + add_write_gsb_command_template(shell, openfpga_setup_cmd_class, + write_gsb_dependent_cmds, hidden); + + /******************************************* + * Command 'check_netlist_naming_conflict' + */ + /* The 'check_netlist_naming_conflict' command should NOT be executed before + * 'vpr' */ + std::vector nlist_naming_dependent_cmds; + nlist_naming_dependent_cmds.push_back(vpr_cmd_id); + add_check_netlist_naming_conflict_command_template( + shell, openfpga_setup_cmd_class, nlist_naming_dependent_cmds, hidden); + + /******************************** + * Command 'pb_pin_fixup' + */ + /* The 'pb_pin_fixup' command should NOT be executed before + * 'read_openfpga_arch' and 'vpr' */ + std::vector pb_pin_fixup_dependent_cmds; + pb_pin_fixup_dependent_cmds.push_back(read_arch_cmd_id); + pb_pin_fixup_dependent_cmds.push_back(vpr_cmd_id); + add_pb_pin_fixup_command_template(shell, openfpga_setup_cmd_class, + pb_pin_fixup_dependent_cmds, hidden); + + /******************************** + * Command 'lut_truth_table_fixup' + */ + /* The 'lut_truth_table_fixup' command should NOT be executed before + * 'read_openfpga_arch' and 'vpr' */ + std::vector lut_tt_fixup_dependent_cmds; + lut_tt_fixup_dependent_cmds.push_back(read_arch_cmd_id); + lut_tt_fixup_dependent_cmds.push_back(vpr_cmd_id); + add_lut_truth_table_fixup_command_template( + shell, openfpga_setup_cmd_class, lut_tt_fixup_dependent_cmds, hidden); + /******************************** + * Command 'build_fabric' + */ + /* The 'build_fabric' command should NOT be executed before + * 'link_openfpga_arch' */ + std::vector build_fabric_dependent_cmds; + build_fabric_dependent_cmds.push_back(link_arch_cmd_id); + ShellCommandId build_fabric_cmd_id = add_build_fabric_command_template( + shell, openfpga_setup_cmd_class, build_fabric_dependent_cmds, hidden); + + /******************************** + * Command 'write_fabric_hierarchy' + */ + /* The 'write_fabric_hierarchy' command should NOT be executed before + * 'build_fabric' */ + std::vector write_fabric_hie_dependent_cmds; + write_fabric_hie_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_fabric_hierarchy_command_template( + shell, openfpga_setup_cmd_class, write_fabric_hie_dependent_cmds, hidden); + + /******************************** + * Command 'write_fabric_io_info' + */ + /* The 'write_fabric_io_info' command should NOT be executed before + * 'build_fabric' */ + std::vector cmd_dependency_write_fabric_io_info; + cmd_dependency_write_fabric_io_info.push_back(build_fabric_cmd_id); + add_write_fabric_io_info_command_template( + shell, openfpga_setup_cmd_class, cmd_dependency_write_fabric_io_info, + hidden); +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_spice.h b/openfpga/src/base/openfpga_spice.h deleted file mode 100644 index 83d3bcdb2..000000000 --- a/openfpga/src/base/openfpga_spice.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef OPENFPGA_SPICE_H -#define OPENFPGA_SPICE_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int write_fabric_spice(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_spice_command.cpp b/openfpga/src/base/openfpga_spice_command.cpp index d3c512311..b7aaf243e 100644 --- a/openfpga/src/base/openfpga_spice_command.cpp +++ b/openfpga/src/base/openfpga_spice_command.cpp @@ -1,94 +1,12 @@ -/******************************************************************** - * Add commands to the OpenFPGA shell interface, - * in purpose of generate SPICE netlists modeling the full FPGA fabric - * This is one of the core engine of openfpga, including: - * - generate_fabric_spice : generate Verilog netlists about FPGA fabric - * - TODO: generate_spice_top_testbench : generate SPICE testbenches for - *top-level module - * - TODO: generate_spice_grid_testbench : generate SPICE testbenches for grids - * - TODO: generate_spice_cb_testbench : generate SPICE testbenches for - *connection blocks - * - TODO: generate_spice_sb_testbench : generate SPICE testbenches for switch - *blocks - * - TODO: generate_spice_lut_testbench : generate SPICE testbenches for Look-Up - *Tables - * - TODO: generate_spice_hard_logic_testbench : generate SPICE testbenches for - *all the hard logics - * - TODO: generate_spice_local_routing_testbench : generate SPICE testbenches - *for local routing - * - TODO: generate_spice_cb_routing_testbench : generate SPICE testbenches for - *routing circuit inside connection blocks - * - TODO: generate_spice_sb_routing_testbench : generate SPICE testbenches for - *routing circuit inside switch blocks - *******************************************************************/ #include "openfpga_spice_command.h" -#include "openfpga_spice.h" +#include "openfpga_spice_command_template.h" /* begin namespace openfpga */ namespace openfpga { -/******************************************************************** - * - Add a command to Shell environment: generate fabric Verilog - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_fabric_spice_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_fabric_spice"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the output directory for SPICE netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "Use explicit port mapping in Verilog netlists"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'write_fabric_spice' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate SPICE netlists modeling full FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_fabric_spice); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - void add_openfpga_spice_commands(openfpga::Shell& shell) { - /* Get the unique id of 'build_fabric' command which is to be used in creating - * the dependency graph */ - const ShellCommandId& build_fabric_cmd_id = - shell.command(std::string("build_fabric")); - - /* Add a new class of commands */ - ShellCommandClassId openfpga_spice_cmd_class = - shell.add_command_class("FPGA-SPICE"); - - /******************************** - * Command 'write_fabric_spice' - */ - /* The 'write_fabric_spice' command should NOT be executed before - * 'build_fabric' */ - std::vector fabric_spice_dependent_cmds; - fabric_spice_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_fabric_spice_command(shell, openfpga_spice_cmd_class, - fabric_spice_dependent_cmds); - - /******************************** - * TODO: Command 'write_spice_top_testbench' - */ - /* The command 'write_spice_top_testbench' should NOT be executed before - * 'build_fabric' */ + add_spice_command_templates(shell); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_spice_command_template.h b/openfpga/src/base/openfpga_spice_command_template.h new file mode 100644 index 000000000..a5b1eb740 --- /dev/null +++ b/openfpga/src/base/openfpga_spice_command_template.h @@ -0,0 +1,101 @@ +#ifndef OPENFPGA_SPICE_COMMAND_TEMPLATE_H +#define OPENFPGA_SPICE_COMMAND_TEMPLATE_H + +/******************************************************************** + * Add commands to the OpenFPGA shell interface, + * in purpose of generate SPICE netlists modeling the full FPGA fabric + * This is one of the core engine of openfpga, including: + * - generate_fabric_spice : generate Verilog netlists about FPGA fabric + * - TODO: generate_spice_top_testbench : generate SPICE testbenches for + *top-level module + * - TODO: generate_spice_grid_testbench : generate SPICE testbenches for grids + * - TODO: generate_spice_cb_testbench : generate SPICE testbenches for + *connection blocks + * - TODO: generate_spice_sb_testbench : generate SPICE testbenches for switch + *blocks + * - TODO: generate_spice_lut_testbench : generate SPICE testbenches for Look-Up + *Tables + * - TODO: generate_spice_hard_logic_testbench : generate SPICE testbenches for + *all the hard logics + * - TODO: generate_spice_local_routing_testbench : generate SPICE testbenches + *for local routing + * - TODO: generate_spice_cb_routing_testbench : generate SPICE testbenches for + *routing circuit inside connection blocks + * - TODO: generate_spice_sb_routing_testbench : generate SPICE testbenches for + *routing circuit inside switch blocks + *******************************************************************/ +#include "openfpga_spice_template.h" +#include "shell.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * - Add a command to Shell environment: generate fabric Verilog + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_spice_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_fabric_spice"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the output directory for SPICE netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "Use explicit port mapping in Verilog netlists"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'write_fabric_spice' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate SPICE netlists modeling full FPGA fabric", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_fabric_spice_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +template +void add_spice_command_templates(openfpga::Shell& shell, + const bool& hidden = false) { + /* Get the unique id of 'build_fabric' command which is to be used in creating + * the dependency graph */ + const ShellCommandId& build_fabric_cmd_id = + shell.command(std::string("build_fabric")); + + /* Add a new class of commands */ + ShellCommandClassId openfpga_spice_cmd_class = + shell.add_command_class("FPGA-SPICE"); + + /******************************** + * Command 'write_fabric_spice' + */ + /* The 'write_fabric_spice' command should NOT be executed before + * 'build_fabric' */ + std::vector fabric_spice_dependent_cmds; + fabric_spice_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_fabric_spice_command_template( + shell, openfpga_spice_cmd_class, fabric_spice_dependent_cmds, hidden); + + /******************************** + * TODO: Command 'write_spice_top_testbench' + */ + /* The command 'write_spice_top_testbench' should NOT be executed before + * 'build_fabric' */ +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_spice.cpp b/openfpga/src/base/openfpga_spice_template.h similarity index 74% rename from openfpga/src/base/openfpga_spice.cpp rename to openfpga/src/base/openfpga_spice_template.h index f18ae76c5..31fe3cfa4 100644 --- a/openfpga/src/base/openfpga_spice.cpp +++ b/openfpga/src/base/openfpga_spice_template.h @@ -1,26 +1,23 @@ -/******************************************************************** - * This file includes functions to compress the hierachy of routing architecture - *******************************************************************/ -/* Headers from vtrutil library */ +#ifndef OPENFPGA_SPICE_TEMPLATE_H +#define OPENFPGA_SPICE_TEMPLATE_H + +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "globals.h" +#include "spice_api.h" #include "vtr_log.h" #include "vtr_time.h" -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" -#include "openfpga_spice.h" -#include "spice_api.h" - -/* Include global variables of VPR */ -#include "globals.h" - /* begin namespace openfpga */ namespace openfpga { /******************************************************************** * A wrapper function to call the fabric SPICE generator of FPGA-SPICE *******************************************************************/ -int write_fabric_spice(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int write_fabric_spice_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); @@ -47,3 +44,5 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx, const Command& cmd, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_verilog.h b/openfpga/src/base/openfpga_verilog.h deleted file mode 100644 index 34b967d0a..000000000 --- a/openfpga/src/base/openfpga_verilog.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef OPENFPGA_VERILOG_H -#define OPENFPGA_VERILOG_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int write_full_testbench(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, const CommandContext& cmd_context); - -int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 6ce1ea193..fd9459865 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -7,445 +7,13 @@ *******************************************************************/ #include "openfpga_verilog_command.h" -#include "openfpga_verilog.h" +#include "openfpga_verilog_command_template.h" /* begin namespace openfpga */ namespace openfpga { -/******************************************************************** - * - Add a command to Shell environment: generate fabric Verilog - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_fabric_verilog_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_fabric_verilog"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the output directory for Verilog netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "Use explicit port mapping in Verilog netlists"); - - /* Add an option '--include_timing' */ - shell_cmd.add_option("include_timing", false, - "Enable timing annotation in Verilog netlists"); - - /* Add an option '--print_user_defined_template' */ - shell_cmd.add_option( - "print_user_defined_template", false, - "Generate a template Verilog files for user-defined circuit models"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* Add an option '--use_relative_path' */ - shell_cmd.add_option( - "use_relative_path", false, - "Force to use relative path in netlists when including other netlists"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'write_fabric_verilog' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate Verilog netlists modeling full FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - add a command to shell environment: write full testbench - * - add associated options - * - add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_full_testbench_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_full_testbench"); - - /* add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "specify the output directory for hdl netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* add an option '--bitstream'*/ - CommandOptionId bitstream_opt = shell_cmd.add_option( - "bitstream", true, "specify the bitstream to be loaded in the testbench"); - shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING); - - /* add an option '--fabric_netlist_file_path'*/ - CommandOptionId fabric_netlist_opt = - shell_cmd.add_option("fabric_netlist_file_path", false, - "specify the file path to the fabric hdl netlist"); - shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); - - /* add an option '--pin_constraints_file in short '-pcf' */ - CommandOptionId pcf_opt = - shell_cmd.add_option("pin_constraints_file", false, - "specify the file path to the pin constraints"); - shell_cmd.set_option_short_name(pcf_opt, "pcf"); - shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); - - /* add an option '--bus_group_file in short '-bgf' */ - CommandOptionId bgf_opt = shell_cmd.add_option( - "bus_group_file", false, "specify the file path to the group pins to bus"); - shell_cmd.set_option_short_name(bgf_opt, "bgf"); - shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); - - /* add an option '--reference_benchmark_file_path'*/ - CommandOptionId ref_bm_opt = shell_cmd.add_option( - "reference_benchmark_file_path", false, - "specify the file path to the reference verilog netlist. If specified, the " - "testbench will include self-checking codes"); - shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); - - /* add an option '--fast_configuration' */ - shell_cmd.add_option( - "fast_configuration", false, - "reduce the period of configuration by skip certain data points"); - - /* add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "use explicit port mapping in verilog netlists"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--no_self_checking' */ - shell_cmd.add_option( - "no_self_checking", false, - "Do not generate self-checking codes for Verilog testbenches."); - - /* add an option '--include_signal_init' */ - shell_cmd.add_option("include_signal_init", false, - "initialize all the signals in verilog testbenches"); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* Add an option '--use_relative_path' */ - shell_cmd.add_option( - "use_relative_path", false, - "Force to use relative path in netlists when including other netlists"); - - /* add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "enable verbose output"); - - /* add command to the shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate full testbenches for an fpga fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_full_testbench); - - /* add command dependency to the shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - add a command to shell environment: write preconfigured fabric wrapper - * - add associated options - * - add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_preconfigured_fabric_wrapper"); - - /* add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "specify the output directory for hdl netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* add an option '--fabric_netlist_file_path'*/ - CommandOptionId fabric_netlist_opt = - shell_cmd.add_option("fabric_netlist_file_path", false, - "specify the file path to the fabric hdl netlist"); - shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); - - /* add an option '--pin_constraints_file in short '-pcf' */ - CommandOptionId pcf_opt = - shell_cmd.add_option("pin_constraints_file", false, - "specify the file path to the pin constraints"); - shell_cmd.set_option_short_name(pcf_opt, "pcf"); - shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); - - /* add an option '--bus_group_file in short '-bgf' */ - CommandOptionId bgf_opt = shell_cmd.add_option( - "bus_group_file", false, "specify the file path to the group pins to bus"); - shell_cmd.set_option_short_name(bgf_opt, "bgf"); - shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); - - /* add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "use explicit port mapping in verilog netlists"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--embed_bitstream' */ - CommandOptionId embed_bitstream_opt = - shell_cmd.add_option("embed_bitstream", false, - "Embed bitstream to the Verilog wrapper netlist; This " - "may cause a large netlist file size"); - shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING); - - /* add an option '--include_signal_init' */ - shell_cmd.add_option("include_signal_init", false, - "initialize all the signals in verilog testbenches"); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "enable verbose output"); - - /* add command to the shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate a wrapper for a pre-configured fpga fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, - write_preconfigured_fabric_wrapper); - - /* add command dependency to the shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write preconfigured testbench - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_preconfigured_testbench_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_preconfigured_testbench"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the output directory for HDL netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* add an option '--fabric_netlist_file_path'*/ - CommandOptionId fabric_netlist_opt = - shell_cmd.add_option("fabric_netlist_file_path", false, - "specify the file path to the fabric hdl netlist"); - shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); - - /* Add an option '--pin_constraints_file in short '-pcf' */ - CommandOptionId pcf_opt = - shell_cmd.add_option("pin_constraints_file", false, - "Specify the file path to the pin constraints"); - shell_cmd.set_option_short_name(pcf_opt, "pcf"); - shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); - - /* add an option '--bus_group_file in short '-bgf' */ - CommandOptionId bgf_opt = shell_cmd.add_option( - "bus_group_file", false, "specify the file path to the group pins to bus"); - shell_cmd.set_option_short_name(bgf_opt, "bgf"); - shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); - - /* Add an option '--reference_benchmark_file_path'*/ - CommandOptionId ref_bm_opt = shell_cmd.add_option( - "reference_benchmark_file_path", false, - "Specify the file path to the reference Verilog netlist. If specified, the " - "testbench will include self-checking codes"); - shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); - - /* Add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "Use explicit port mapping in Verilog netlists"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* Add an option '--use_relative_path' */ - shell_cmd.add_option( - "use_relative_path", false, - "Force to use relative path in netlists when including other netlists"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate testbenches for a preconfigured FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, - write_preconfigured_testbench); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write simulation task info - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_simulation_task_info_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_simulation_task_info"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, - "Specify the file path to output simulation-related information"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--hdl_dir'*/ - CommandOptionId hdl_dir_opt = shell_cmd.add_option( - "hdl_dir", true, - "Specify the directory path where HDL netlists are created"); - shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING); - - /* Add an option '--reference_benchmark_file_path'*/ - CommandOptionId ref_bm_opt = shell_cmd.add_option( - "reference_benchmark_file_path", false, - "Specify the file path to the reference Verilog netlist. If specified, the " - "testbench will include self-checking codes"); - shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); - - /* Add an option '--testbench_type'*/ - CommandOptionId tb_type_opt = shell_cmd.add_option( - "testbench_type", false, - "Specify the type of testbenches to be considered. Different testbenches " - "have different simulation parameters."); - shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING); - - /* Add an option '--time_unit' */ - CommandOptionId time_unit_opt = - shell_cmd.add_option("time_unit", false, - "Specify the time unit to be used in HDL simulation. " - "Acceptable is [a|f|p|n|u|m|k|M]s"); - shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate an interchangable simulation task configuration file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_simulation_task_info); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - void add_openfpga_verilog_commands(openfpga::Shell& shell) { - /* Get the unique id of 'build_fabric' command which is to be used in creating - * the dependency graph */ - const ShellCommandId& build_fabric_cmd_id = - shell.command(std::string("build_fabric")); - - /* Add a new class of commands */ - ShellCommandClassId openfpga_verilog_cmd_class = - shell.add_command_class("FPGA-Verilog"); - - /******************************** - * Command 'write_fabric_verilog' - */ - /* The 'write_fabric_verilog' command should NOT be executed before - * 'build_fabric' */ - std::vector fabric_verilog_dependent_cmds; - fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_fabric_verilog_command(shell, openfpga_verilog_cmd_class, - fabric_verilog_dependent_cmds); - - /******************************** - * Command 'write_full_testbench' - */ - /* The command 'write_full_testbench' should NOT be executed before - * 'build_fabric' */ - std::vector full_testbench_dependent_cmds; - full_testbench_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_full_testbench_command(shell, openfpga_verilog_cmd_class, - full_testbench_dependent_cmds); - - /******************************** - * Command 'write_preconfigured_fabric_wrapper' - */ - /* The command 'write_preconfigured_fabric_wrapper' should NOT be executed - * before 'build_fabric' */ - std::vector preconfig_wrapper_dependent_cmds; - preconfig_wrapper_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_preconfigured_fabric_wrapper_command( - shell, openfpga_verilog_cmd_class, preconfig_wrapper_dependent_cmds); - - /******************************** - * Command 'write_preconfigured_testbench' - */ - /* The command 'write_preconfigured_testbench' should NOT be executed before - * 'build_fabric' */ - std::vector preconfig_testbench_dependent_cmds; - preconfig_testbench_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_preconfigured_testbench_command( - shell, openfpga_verilog_cmd_class, preconfig_testbench_dependent_cmds); - - /******************************** - * Command 'write_simulation_task_info' - */ - /* The command 'write_simulation_task_info' should NOT be executed before - * 'build_fabric' */ - std::vector sim_task_info_dependent_cmds; - sim_task_info_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_simulation_task_info_command( - shell, openfpga_verilog_cmd_class, sim_task_info_dependent_cmds); + add_verilog_command_templates(shell); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h new file mode 100644 index 000000000..266afc6d8 --- /dev/null +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -0,0 +1,462 @@ +#ifndef OPENFPGA_VERILOG_COMMAND_TEMPLATE_H +#define OPENFPGA_VERILOG_COMMAND_TEMPLATE_H +/******************************************************************** + * Add commands to the OpenFPGA shell interface, + * in purpose of generate Verilog netlists modeling the full FPGA fabric + * This is one of the core engine of openfpga, including: + * - generate_fabric_verilog : generate Verilog netlists about FPGA fabric + * - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches + *******************************************************************/ +#include "openfpga_verilog_template.h" +#include "shell.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * - Add a command to Shell environment: generate fabric Verilog + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_verilog_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_fabric_verilog"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the output directory for Verilog netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "Use explicit port mapping in Verilog netlists"); + + /* Add an option '--include_timing' */ + shell_cmd.add_option("include_timing", false, + "Enable timing annotation in Verilog netlists"); + + /* Add an option '--print_user_defined_template' */ + shell_cmd.add_option( + "print_user_defined_template", false, + "Generate a template Verilog files for user-defined circuit models"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* Add an option '--use_relative_path' */ + shell_cmd.add_option( + "use_relative_path", false, + "Force to use relative path in netlists when including other netlists"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'write_fabric_verilog' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate Verilog netlists modeling full FPGA fabric", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_fabric_verilog_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - add a command to shell environment: write full testbench + * - add associated options + * - add command dependency + *******************************************************************/ +template +ShellCommandId add_write_full_testbench_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_full_testbench"); + + /* add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "specify the output directory for hdl netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--bitstream'*/ + CommandOptionId bitstream_opt = shell_cmd.add_option( + "bitstream", true, "specify the bitstream to be loaded in the testbench"); + shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = + shell_cmd.add_option("fabric_netlist_file_path", false, + "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = + shell_cmd.add_option("pin_constraints_file", false, + "specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--bus_group_file in short '-bgf' */ + CommandOptionId bgf_opt = shell_cmd.add_option( + "bus_group_file", false, "specify the file path to the group pins to bus"); + shell_cmd.set_option_short_name(bgf_opt, "bgf"); + shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); + + /* add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option( + "reference_benchmark_file_path", false, + "specify the file path to the reference verilog netlist. If specified, the " + "testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* add an option '--fast_configuration' */ + shell_cmd.add_option( + "fast_configuration", false, + "reduce the period of configuration by skip certain data points"); + + /* add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "use explicit port mapping in verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--no_self_checking' */ + shell_cmd.add_option( + "no_self_checking", false, + "Do not generate self-checking codes for Verilog testbenches."); + + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, + "initialize all the signals in verilog testbenches"); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* Add an option '--use_relative_path' */ + shell_cmd.add_option( + "use_relative_path", false, + "Force to use relative path in netlists when including other netlists"); + + /* add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "enable verbose output"); + + /* add command to the shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate full testbenches for an fpga fabric", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_full_testbench_template); + + /* add command dependency to the shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - add a command to shell environment: write preconfigured fabric wrapper + * - add associated options + * - add command dependency + *******************************************************************/ +template +ShellCommandId add_write_preconfigured_fabric_wrapper_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_preconfigured_fabric_wrapper"); + + /* add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "specify the output directory for hdl netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = + shell_cmd.add_option("fabric_netlist_file_path", false, + "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = + shell_cmd.add_option("pin_constraints_file", false, + "specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--bus_group_file in short '-bgf' */ + CommandOptionId bgf_opt = shell_cmd.add_option( + "bus_group_file", false, "specify the file path to the group pins to bus"); + shell_cmd.set_option_short_name(bgf_opt, "bgf"); + shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); + + /* add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "use explicit port mapping in verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--embed_bitstream' */ + CommandOptionId embed_bitstream_opt = + shell_cmd.add_option("embed_bitstream", false, + "Embed bitstream to the Verilog wrapper netlist; This " + "may cause a large netlist file size"); + shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING); + + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, + "initialize all the signals in verilog testbenches"); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "enable verbose output"); + + /* add command to the shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate a wrapper for a pre-configured fpga fabric", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function( + shell_cmd_id, write_preconfigured_fabric_wrapper_template); + + /* add command dependency to the shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write preconfigured testbench + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_preconfigured_testbench_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_preconfigured_testbench"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the output directory for HDL netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = + shell_cmd.add_option("fabric_netlist_file_path", false, + "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* Add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = + shell_cmd.add_option("pin_constraints_file", false, + "Specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--bus_group_file in short '-bgf' */ + CommandOptionId bgf_opt = shell_cmd.add_option( + "bus_group_file", false, "specify the file path to the group pins to bus"); + shell_cmd.set_option_short_name(bgf_opt, "bgf"); + shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); + + /* Add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option( + "reference_benchmark_file_path", false, + "Specify the file path to the reference Verilog netlist. If specified, the " + "testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* Add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "Use explicit port mapping in Verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* Add an option '--use_relative_path' */ + shell_cmd.add_option( + "use_relative_path", false, + "Force to use relative path in netlists when including other netlists"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate testbenches for a preconfigured FPGA fabric", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_preconfigured_testbench_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write simulation task info + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_simulation_task_info_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_simulation_task_info"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, + "Specify the file path to output simulation-related information"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--hdl_dir'*/ + CommandOptionId hdl_dir_opt = shell_cmd.add_option( + "hdl_dir", true, + "Specify the directory path where HDL netlists are created"); + shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING); + + /* Add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option( + "reference_benchmark_file_path", false, + "Specify the file path to the reference Verilog netlist. If specified, the " + "testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* Add an option '--testbench_type'*/ + CommandOptionId tb_type_opt = shell_cmd.add_option( + "testbench_type", false, + "Specify the type of testbenches to be considered. Different testbenches " + "have different simulation parameters."); + shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING); + + /* Add an option '--time_unit' */ + CommandOptionId time_unit_opt = + shell_cmd.add_option("time_unit", false, + "Specify the time unit to be used in HDL simulation. " + "Acceptable is [a|f|p|n|u|m|k|M]s"); + shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate an interchangable simulation task configuration file", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_simulation_task_info_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +template +void add_verilog_command_templates(openfpga::Shell& shell, + const bool& hidden = false) { + /* Get the unique id of 'build_fabric' command which is to be used in creating + * the dependency graph */ + const ShellCommandId& build_fabric_cmd_id = + shell.command(std::string("build_fabric")); + + /* Add a new class of commands */ + ShellCommandClassId openfpga_verilog_cmd_class = + shell.add_command_class("FPGA-Verilog"); + + /******************************** + * Command 'write_fabric_verilog' + */ + /* The 'write_fabric_verilog' command should NOT be executed before + * 'build_fabric' */ + std::vector fabric_verilog_dependent_cmds; + fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_fabric_verilog_command_template( + shell, openfpga_verilog_cmd_class, fabric_verilog_dependent_cmds, hidden); + + /******************************** + * Command 'write_full_testbench' + */ + /* The command 'write_full_testbench' should NOT be executed before + * 'build_fabric' */ + std::vector full_testbench_dependent_cmds; + full_testbench_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_full_testbench_command_template( + shell, openfpga_verilog_cmd_class, full_testbench_dependent_cmds, hidden); + + /******************************** + * Command 'write_preconfigured_fabric_wrapper' + */ + /* The command 'write_preconfigured_fabric_wrapper' should NOT be executed + * before 'build_fabric' */ + std::vector preconfig_wrapper_dependent_cmds; + preconfig_wrapper_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_preconfigured_fabric_wrapper_command_template( + shell, openfpga_verilog_cmd_class, preconfig_wrapper_dependent_cmds, + hidden); + + /******************************** + * Command 'write_preconfigured_testbench' + */ + /* The command 'write_preconfigured_testbench' should NOT be executed before + * 'build_fabric' */ + std::vector preconfig_testbench_dependent_cmds; + preconfig_testbench_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_preconfigured_testbench_command_template( + shell, openfpga_verilog_cmd_class, preconfig_testbench_dependent_cmds, + hidden); + + /******************************** + * Command 'write_simulation_task_info' + */ + /* The command 'write_simulation_task_info' should NOT be executed before + * 'build_fabric' */ + std::vector sim_task_info_dependent_cmds; + sim_task_info_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_simulation_task_info_command_template( + shell, openfpga_verilog_cmd_class, sim_task_info_dependent_cmds, hidden); +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog_template.h similarity index 93% rename from openfpga/src/base/openfpga_verilog.cpp rename to openfpga/src/base/openfpga_verilog_template.h index 90bd48eb1..3f042ddcc 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -1,35 +1,29 @@ +#ifndef OPENFPGA_VERILOG_TEMPLATE_H +#define OPENFPGA_VERILOG_TEMPLATE_H + /******************************************************************** * This file includes functions to compress the hierachy of routing architecture *******************************************************************/ -/* Headers from vtrutil library */ +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "globals.h" +#include "openfpga_scale.h" +#include "read_xml_bus_group.h" +#include "read_xml_pin_constraints.h" +#include "verilog_api.h" #include "vtr_log.h" #include "vtr_time.h" -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" - -/* Headers from openfpgautil library */ -#include "openfpga_scale.h" -#include "openfpga_verilog.h" -#include "verilog_api.h" - -/* Headers from pcf library */ -#include "read_xml_pin_constraints.h" - -/* Headers from bgf library */ -#include "read_xml_bus_group.h" - -/* Include global variables of VPR */ -#include "globals.h" - /* begin namespace openfpga */ namespace openfpga { /******************************************************************** * A wrapper function to call the fabric Verilog generator of FPGA-Verilog *******************************************************************/ -int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); @@ -77,9 +71,9 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, const Command& cmd, /******************************************************************** * A wrapper function to call the full testbench generator of FPGA-Verilog *******************************************************************/ -int write_full_testbench(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_bitstream = cmd.option("bitstream"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); @@ -150,9 +144,10 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, * A wrapper function to call the preconfigured wrapper generator of *FPGA-Verilog *******************************************************************/ -int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_preconfigured_fabric_wrapper_template( + const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); @@ -216,9 +211,10 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, * A wrapper function to call the preconfigured testbench generator of *FPGA-Verilog *******************************************************************/ -int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_preconfigured_testbench_template(const T& openfpga_ctx, + const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_bgf = cmd.option("bus_group_file"); @@ -278,9 +274,10 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, * A wrapper function to call the simulation task information generator of *FPGA-Verilog *******************************************************************/ -int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_simulation_task_info_template(const T& openfpga_ctx, + const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_file = cmd.option("file"); CommandOptionId opt_hdl_dir = cmd.option("hdl_dir"); CommandOptionId opt_reference_benchmark = @@ -337,3 +334,5 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_write_gsb.h b/openfpga/src/base/openfpga_write_gsb.h deleted file mode 100644 index a059724cd..000000000 --- a/openfpga/src/base/openfpga_write_gsb.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef OPENFPGA_WRITE_GSB_H -#define OPENFPGA_WRITE_GSB_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int write_gsb(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_write_gsb.cpp b/openfpga/src/base/openfpga_write_gsb_template.h similarity index 88% rename from openfpga/src/base/openfpga_write_gsb.cpp rename to openfpga/src/base/openfpga_write_gsb_template.h index be74c2a11..bc11cee14 100644 --- a/openfpga/src/base/openfpga_write_gsb.cpp +++ b/openfpga/src/base/openfpga_write_gsb_template.h @@ -1,18 +1,16 @@ +#ifndef OPENFPGA_WRITE_GSB_TEMPLATE_H +#define OPENFPGA_WRITE_GSB_TEMPLATE_H /******************************************************************** * This file includes functions to compress the hierachy of routing architecture *******************************************************************/ -/* Headers from vtrutil library */ +#include "command.h" +#include "command_context.h" +#include "command_exit_codes.h" +#include "globals.h" #include "vtr_log.h" #include "vtr_time.h" - -/* Headers from openfpgashell library */ -#include "command_exit_codes.h" -#include "openfpga_write_gsb.h" #include "write_xml_device_rr_gsb.h" -/* Include global variables of VPR */ -#include "globals.h" - /* begin namespace openfpga */ namespace openfpga { @@ -20,8 +18,9 @@ namespace openfpga { * Write internal structrure of all the General Switch Blocks (GSBs) * to an XML file *******************************************************************/ -int write_gsb(const OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +template +int write_gsb_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction @@ -60,3 +59,5 @@ int write_gsb(const OpenfpgaContext& openfpga_ctx, const Command& cmd, } } /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/utils/openfpga_rr_graph_support.cpp b/openfpga/src/utils/openfpga_rr_graph_support.cpp new file mode 100644 index 000000000..19a44cddc --- /dev/null +++ b/openfpga/src/utils/openfpga_rr_graph_support.cpp @@ -0,0 +1,38 @@ +#include "openfpga_rr_graph_support.h" + +#include "vtr_log.h" + +namespace openfpga { + +/******************************************************************** + * A function to identify if the routing resource graph generated by + * VPR is support by OpenFPGA + * - Currently we only support uni-directional + * It means every routing tracks must have a direction + *******************************************************************/ +bool is_vpr_rr_graph_supported(const RRGraphView& rr_graph) { + /* Check if the rr_graph is uni-directional*/ + for (const RRNodeId& node : rr_graph.nodes()) { + if (CHANX != rr_graph.node_type(node) && + CHANY != rr_graph.node_type(node)) { + continue; + } + if (Direction::BIDIR == rr_graph.node_direction(node)) { + VTR_LOG_ERROR( + "Routing resource graph is bi-directional. OpenFPGA currently supports " + "uni-directional routing architecture only.\n"); + return false; + } + if (Direction::NONE == rr_graph.node_direction(node)) { + VTR_LOG_ERROR( + "Routing resource graph contains routing tracks which has not specific " + "direction. OpenFPGA currently supports uni-directional routing " + "architecture only.\n"); + return false; + } + } + + return true; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/utils/openfpga_rr_graph_support.h b/openfpga/src/utils/openfpga_rr_graph_support.h new file mode 100644 index 000000000..b9b1eb996 --- /dev/null +++ b/openfpga/src/utils/openfpga_rr_graph_support.h @@ -0,0 +1,13 @@ +#ifndef OPENFPGA_RR_GRAPH_SUPPORT_H +#define OPENFPGA_RR_GRAPH_SUPPORT_H + +#include "rr_graph_view.h" + +/* begin namespace openfpga */ +namespace openfpga { + +bool is_vpr_rr_graph_supported(const RRGraphView& rr_graph); + +} /* end namespace openfpga */ + +#endif