riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] code format

This commit is contained in:
tangxifan 2023-04-23 16:49:19 +08:00
parent ba90f5020b
commit 1ba3c56cf3
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
openfpga/src/utils/module_manager_utils.cpp
View File

@ -2234,10 +2234,11 @@ void add_module_global_input_ports_from_child_modules(
module_manager.module_port(child, child_global_port_id); module_manager.module_port(child, child_global_port_id);
/* Skip if it is in the ignore list */ /* Skip if it is in the ignore list */
if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(), if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(),
child_global_port.get_name()) != port_name_to_ignore.end()) { child_global_port.get_name()) !=
port_name_to_ignore.end()) {
continue; continue;
} }
/* Search in the global port list to be added, find the port id */ /* Search in the global port list to be added, find the port id */
std::vector<BasicPort>::iterator it = std::vector<BasicPort>::iterator it =
std::find(global_ports_to_add.begin(), global_ports_to_add.end(), std::find(global_ports_to_add.begin(), global_ports_to_add.end(),
@ -2266,7 +2267,8 @@ void add_module_global_input_ports_from_child_modules(
module_manager.module_port(child, child_global_port_id); module_manager.module_port(child, child_global_port_id);
/* Skip if it is in the ignore list */ /* Skip if it is in the ignore list */
if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(), if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(),
child_global_port.get_name()) != port_name_to_ignore.end()) { child_global_port.get_name()) !=
port_name_to_ignore.end()) {
continue; continue;
} }