riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' into master

This commit is contained in:
chungshien 2024-03-06 03:49:17 -08:00 committed by GitHub
parent 1874695552 a477fdff14
commit 1ba287323b
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
3 changed files with 18 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
VERSION.md
View File

@ -1 +1 @@
1.2.1947
1.2.1957

16
libs/libpcf/src/base/pcf2place.cpp
View File

@ -41,6 +41,8 @@ int pcf2place(const PcfData& pcf_data,
VTR_LOG("PCF basic check passed\n");
}
/* Map from location to net */
std::map<std::array<size_t, 3>, std::string> net_map;
/* Build the I/O place */
for (const PcfIoConstraintId& io_id : pcf_data.io_constraints()) {
/* Find the net name */
@ -102,6 +104,20 @@ int pcf2place(const PcfData& pcf_data,
continue;
}
std::array<size_t, 3> loc = {x, y, z};
auto itr = net_map.find(loc);
if (itr == net_map.end()) {
net_map.insert({loc, net});
} else {
VTR_LOG_ERROR(
"Illegal pin constraint: Two nets '%s' and '%s' are mapped to the I/O "
"pin '%s[%lu]' which belongs to the same coordinate (%ld, %ld, %ld)!\n",
itr->second.c_str(), net.c_str(), int_pin.get_name().c_str(),
int_pin.get_lsb(), x, y, z);
num_err++;
continue;
}
/* Add a fixed prefix to net namei, this is hard coded by VPR */
if (IoPinTable::OUTPUT == pin_direction) {
net = "out:" + net;

2
yosys

@ -1 +1 @@
Subproject commit 91fbd58980e87ad5dc0a5d37c049ffaf5ab243dd
Subproject commit 1e42b4f0f9cc1d2f4097ea632a93be3473b0c2f7