diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml
index c9dc5e65e..370341554 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml
@@ -302,7 +302,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false" concat_wire="true" concat_pass_wire="false">
+  <layout tileable="true" through_channel="false" opin2all_sides="true" concat_wire="true" concat_pass_wire="false">
     <auto_layout aspect_ratio="1.0">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing
index 5d41e33cc..229e43e30 160000
--- a/vtr-verilog-to-routing
+++ b/vtr-verilog-to-routing
@@ -1 +1 @@
-Subproject commit 5d41e33cc89a34d0481550728f855252a63ac704
+Subproject commit 229e43e30bd7a99bf34239179ad957ca6e00f8da