riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

bug fixing for lb router. Add physical mode to default node expanding settings

This commit is contained in:
tangxifan 2020-02-21 11:29:00 -07:00
parent 0b0e00b5f4
commit 1b66e837ba
5 changed files with 66 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
openfpga/src/repack/lb_router.cpp
View File

@ -109,7 +109,7 @@ bool LbRouter::route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) con
t_mode* cur_mode = nullptr;
for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
std::vector<LbRREdgeId> edges = lb_rr_graph.find_edge(rt->current_node, rt->next_nodes[i].current_node);
VTR_ASSERT(0 == edges.size());
VTR_ASSERT(1 == edges.size());
t_mode* new_mode = lb_rr_graph.edge_mode(edges[0]);
if (cur_mode != nullptr && cur_mode != new_mode) {
return true;
@ -165,6 +165,34 @@ void LbRouter::add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, con
lb_net_atom_pins_[net].insert(lb_net_atom_pins_[net].begin(), src_pin);
}
void LbRouter::set_physical_pb_modes(const LbRRGraph& lb_rr_graph,
const VprDeviceAnnotation& device_annotation) {
/* Go through each node in the routing resource graph
* Find the physical mode of each pb_graph_pin that is binded to the node
* For input pins, the physical mode is a mode of its parent pb_type
* For output pins, the physical mode is a mode of the parent pb_type of its parent
*/
for (const LbRRNodeId& node : lb_rr_graph.nodes()) {
t_pb_graph_pin* pb_pin = lb_rr_graph.node_pb_graph_pin(node);
if (nullptr == pb_pin) {
routing_status_[node].mode = nullptr;
} else {
if (IN_PORT == pb_pin->port->type) {
routing_status_[node].mode = device_annotation.physical_mode(pb_pin->parent_node->pb_type);
} else {
VTR_ASSERT(OUT_PORT == pb_pin->port->type);
/* For top-level pb_graph node, the physical mode is nullptr */
if (true == pb_pin->parent_node->is_root()) {
routing_status_[node].mode = nullptr;
} else {
routing_status_[node].mode = device_annotation.physical_mode(pb_pin->parent_node->parent_pb_graph_node->pb_type);
/* TODO: need to think about how to handle INOUT ports !!! */
}
}
}
}
}
bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
const AtomNetlist& atom_nlist,
const int& verbosity) {
@ -263,8 +291,10 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
} else {
--inet;
VTR_LOGV(verbosity < 3,
"Net '%s' is impossible to route within proposed %s cluster\n",
atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(), lb_type_->name);
"Net %lu '%s' is impossible to route within proposed %s cluster\n",
inet,
atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
lb_type_->name);
VTR_LOGV(verbosity < 3,
"\tNet source pin '%s'\n",
lb_rr_graph.node_pb_graph_pin(lb_net_terminals_[NetId(inet)][0])->to_string().c_str());
@ -573,8 +603,11 @@ void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
t_mode* next_mode = routing_status_[enode.node_index].mode;
/* Assume first mode if a mode hasn't been forced. */
if (nullptr == next_mode) {
/* If the node is mapped to a nullptr pb_graph_pin, this is a special SINK. Use nullptr mode */
if (nullptr == lb_rr_graph.node_pb_graph_pin(enode.node_index)) {
next_mode = nullptr;
} else if (true == is_primitive_pb_type(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type)) {
/* For primitive node, we give nullptr as default */
if (true == is_primitive_pb_type(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type)) {
next_mode = nullptr;
} else {
next_mode = &(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type->modes[0]);
@ -614,7 +647,13 @@ void LbRouter::expand_node(const LbRRGraph& lb_rr_graph,
float cur_cost = exp_node.cost;
t_mode* mode = routing_status_[cur_node].mode;
if (nullptr == mode) {
mode = &(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type->modes[0]);
if (nullptr == lb_rr_graph.node_pb_graph_pin(cur_node)) {
mode = nullptr;
} else if (true == is_primitive_pb_type(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type)) {
mode = nullptr;
} else {
mode = &(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type->modes[0]);
}
}
expand_edges(lb_rr_graph, mode, cur_node, cur_cost, net_fanout);

12
openfpga/src/repack/lb_router.h
View File

@ -15,6 +15,7 @@
#include "physical_types.h"
#include "vpr_context.h"
#include "vpr_device_annotation.h"
#include "lb_rr_graph.h"
/********************************************************************
@ -184,6 +185,17 @@ class LbRouter {
void add_net_atom_net_id(const NetId& net, const AtomNetId& atom_net);
void add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, const std::vector<AtomPinId>& terminal_pins);
/* TODO: Initialize all the modes in routing status with the mode set in pb
* This is function used for general purpose packing
*/
/* Set all the modes in routing status with the physical mode defined in device annotation
* This method is used only in repacking for physical logical blocks
* Do NOT use it during the general purpose packing
*/
void set_physical_pb_modes(const LbRRGraph& lb_rr_graph,
const VprDeviceAnnotation& device_annotation);
/**
* Perform routing algorithm on a given logical tile routing resource graph
* Note: the lb_rr_graph must be the same as you initilized the router!!!

5
openfpga/src/repack/repack.cpp
View File

@ -269,6 +269,11 @@ void repack_cluster(const DeviceContext& device_ctx,
clustering_ctx, const_cast<const VprClusteringAnnotation&>(clustering_annotation),
block_id, verbose);
/* Initialize the modes to expand routing trees with the physical modes in device annotation
* This is a must-do before running the routeri in the purpose of repacking!!!
*/
lb_router.set_physical_pb_modes(lb_rr_graph, device_annotation);
/* Run the router */
bool route_success = lb_router.try_route(lb_rr_graph, atom_ctx.nlist, verbose);

2
openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
View File

@ -226,7 +226,7 @@
<port name="in" physical_mode_port="in[0:5]"/>
<port name="out" physical_mode_port="lut6_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

6
openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
View File

@ -237,8 +237,9 @@
</pb_type>
<interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
<direct name="direct2" input="frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
<direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
</interconnect>
</pb_type>
<!-- Define flip-flop -->
@ -251,6 +252,7 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->