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now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML

This commit is contained in:
tangxifan 2020-04-20 21:12:51 -06:00
parent 9761d13eef
commit 1a8968cb37
1 changed files with 39 additions and 0 deletions
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39
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
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@ -334,6 +334,45 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR"));
/* Contrain each routing track inside the connection block */
for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
/* Create a port description for the input */
std::string input_port_name = generate_cb_module_track_port_name(cb_type,
itrack,
IN_PORT);
ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name);
BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
/* Create a port description for the output */
std::string output_port_name = generate_cb_module_track_port_name(cb_type,
itrack,
OUT_PORT);
ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name);
BasicPort output_port = module_manager.module_port(cb_module, output_port_id);
/* Ensure port size matching */
VTR_ASSERT(1 == input_port.get_width());
VTR_ASSERT(input_port.get_width() == output_port.get_width());
/* Connection block routing segment ids for each track */
RRSegmentId segment_id = rr_gsb.get_chan_node_segment(rr_gsb.get_cb_chan_side(cb_type), itrack);
float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal;
/* If we have a zero-delay path to contrain, we will skip unless users want so */
if ( (false == constrain_zero_delay_paths)
&& (0. == routing_segment_delay) ) {
continue;
}
/* Constrain a path with routing segment delay */
print_pnr_sdc_constrain_port2port_timing(fp,
module_manager,
cb_module, input_port_id,
cb_module, output_port_id,
routing_segment_delay);
}
/* Contrain each multiplexers inside the connection block */
std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
for (size_t side = 0; side < cb_sides.size(); ++side) {