From 1a79a556467ae8d9d4d791b94462e168e15635ca Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Nov 2020 11:19:19 -0700
Subject: [PATCH] [HDL] Add DFF cell with reset but only 1 output

---
 .../openfpga_cell_library/verilog/dff.v       | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v
index efbe705c1..99bb50c85 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dff.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v
@@ -57,6 +57,38 @@ end
 
 endmodule //End Of Module
 
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - single output
+//               - asynchronous active high reset
+//-----------------------------------------------------
+module DFFRQ (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+  q_reg <= 1'b0;
+end else begin
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+`else
+  assign Q = 1'bZ;
+`endif
+
+endmodule //End Of Module
+
+
 //-----------------------------------------------------
 // Function    : D-type flip-flop with 
 //               - asynchronous active high reset