From 1a3e0201749c2078cc8dacde28be0d1b1c9f02dc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 19 Aug 2020 20:04:01 -0600 Subject: [PATCH] deploy through channel test case to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index 7ee1a5095..8424475fb 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -81,6 +81,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/p echo -e "Testing Depopulated crossbar in local routing"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs +echo -e "Testing through channels in tileable routing"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel --debug --show_thread_logs + # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail