riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Bitstream] Relax fabric bitstream address check

This commit is contained in:
tangxifan 2021-09-25 12:03:33 -07:00
parent 8b72447dad
commit 1a2a2a6e63
3 changed files with 49 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
View File

@ -194,10 +194,10 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B
}
/* Set BL address */
fabric_bitstream.set_bit_bl_address(fabric_bit, bl_addr_bits_vec);
fabric_bitstream.set_bit_bl_address(fabric_bit, bl_addr_bits_vec, true);
/* Set WL address */
fabric_bitstream.set_bit_wl_address(fabric_bit, wl_addr_bits_vec);
fabric_bitstream.set_bit_wl_address(fabric_bit, wl_addr_bits_vec, true);
/* Set data input */
fabric_bitstream.set_bit_din(fabric_bit, bitstream_manager.bit_value(config_bit));
@ -291,6 +291,28 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
/* Build the bitstream for all the blocks in this region */
FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region();
/* Find the BL/WL port (different region may have different sizes of BL/WLs) */
ModulePortId cur_bl_addr_port;
if (BLWL_PROTOCOL_DECODER == config_protocol.bl_protocol_type()) {
cur_bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
cur_bl_addr_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_BL_PORT_NAME), config_region));
} else {
/* TODO */
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
}
ModulePortId cur_wl_addr_port;
if (BLWL_PROTOCOL_DECODER == config_protocol.wl_protocol_type()) {
cur_wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type()) {
cur_wl_addr_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_WL_PORT_NAME), config_region));
} else {
/* TODO */
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type());
}
BasicPort cur_wl_addr_port_info = module_manager.module_port(top_module, cur_wl_addr_port);
/**************************************************************
* Precompute the BLs and WLs distribution across the FPGA fabric
@ -319,8 +341,8 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
config_region,
config_protocol,
circuit_lib, config_protocol.memory_model(),
bl_addr_port_info.get_width(),
wl_addr_port_info.get_width(),
cur_bl_addr_port_info.get_width(),
cur_wl_addr_port_info.get_width(),
temp_num_bls_cur_tile, bl_start_index_per_tile,
temp_num_wls_cur_tile, wl_start_index_per_tile,
temp_coord,

23
openfpga/src/fpga_bitstream/fabric_bitstream.cpp
View File

@ -139,24 +139,35 @@ FabricBitId FabricBitstream::add_bit(const ConfigBitId& config_bit_id) {
}
void FabricBitstream::set_bit_address(const FabricBitId& bit_id,
const std::vector<char>& address) {
const std::vector<char>& address,
const bool& tolerant_short_address) {
VTR_ASSERT(true == valid_bit_id(bit_id));
VTR_ASSERT(true == use_address_);
VTR_ASSERT(address_length_ == address.size());
if (tolerant_short_address) {
VTR_ASSERT(address_length_ => address.size());
} else {
VTR_ASSERT(address_length_ == address.size());
}
bit_addresses_[bit_id] = address;
}
void FabricBitstream::set_bit_bl_address(const FabricBitId& bit_id,
const std::vector<char>& address) {
set_bit_address(bit_id, address);
const std::vector<char>& address,
const bool& tolerant_short_address) {
set_bit_address(bit_id, address, tolerant_short_address);
}
void FabricBitstream::set_bit_wl_address(const FabricBitId& bit_id,
const std::vector<char>& address) {
const std::vector<char>& address,
const bool& tolerant_short_address) {
VTR_ASSERT(true == valid_bit_id(bit_id));
VTR_ASSERT(true == use_address_);
VTR_ASSERT(true == use_wl_address_);
VTR_ASSERT(wl_address_length_ == address.size());
if (tolerant_short_address) {
VTR_ASSERT(wl_address_length_ => address.size());
} else {
VTR_ASSERT(wl_address_length_ == address.size());
}
bit_wl_addresses_[bit_id] = address;
}

9
openfpga/src/fpga_bitstream/fabric_bitstream.h
View File

@ -135,13 +135,16 @@ class FabricBitstream {
FabricBitId add_bit(const ConfigBitId& config_bit_id);
void set_bit_address(const FabricBitId& bit_id,
const std::vector<char>& address);
const std::vector<char>& address,
const bool& tolerant_short_address = false);
void set_bit_bl_address(const FabricBitId& bit_id,
const std::vector<char>& address);
const std::vector<char>& address,
const bool& tolerant_short_address = false);
void set_bit_wl_address(const FabricBitId& bit_id,
const std::vector<char>& address);
const std::vector<char>& address,
const bool& tolerant_short_address = false);
void set_bit_din(const FabricBitId& bit_id,
const char& din);