From 1a1da30ae96402cdc270caf1801692d9c3935272 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 16:46:43 -0600 Subject: [PATCH] fixed a critical bug in using tileable route chan W --- vpr7_x2p/vpr/SRC/base/place_and_route.c | 33 +++++++++---------- .../rr_graph/rr_graph_builder_utils.cpp | 8 ++--- .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 12 +++---- 3 files changed, 24 insertions(+), 29 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index 8c1d410a2..c3351c89c 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -353,21 +353,12 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, low = -1; } - /* Xifan Tang: W estimation for tileable routing architecture */ /* Build the segment inf vector */ std::vector segment_vec; for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) { segment_vec.push_back(segment_inf[iseg]); } - if (TRUE == router_opts.use_tileable_route_chan_width) { - int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); - vpr_printf(TIO_MESSAGE_INFO, - "Adapt routing channel width (%d) to be tileable: %d\n", - current, adapted_W); - current = adapted_W; - } - /* Constraints must be checked to not break rr_graph generator */ if (det_routing_arch.directionality == UNI_DIRECTIONAL) { if (current % 2 != 0) { @@ -390,6 +381,21 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, attempt_count = 0; while (final == -1) { + /* Xifan Tang: W estimation for tileable routing architecture */ + if (TRUE == router_opts.use_tileable_route_chan_width) { + int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); + vpr_printf(TIO_MESSAGE_INFO, + "Adapt routing channel width (%d) to be tileable: %d\n", + current, adapted_W); + current = adapted_W; + } + /* Do a early exit when the current equals to high or low, + * This means that the current W has been tried already. We just return a final value (high) + */ + if ( (current == high) || (current == low) ) { + final = high; + break; + } vpr_printf(TIO_MESSAGE_INFO, "Using low: %d, high: %d, current: %d\n", low, high, current); fflush(stdout); @@ -509,15 +515,6 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, } } current = current + current % udsd_multiplier; - - /* Xifan Tang: W estimation for tileable routing architecture */ - if (TRUE == router_opts.use_tileable_route_chan_width) { - int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); - vpr_printf(TIO_MESSAGE_INFO, - "Adapt routing channel width (%d) to be tileable: %d\n", - current, adapted_W); - current = adapted_W; - } } /* The binary search above occassionally does not find the minimum * diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp index d7d2fcd34..6752def9e 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp @@ -625,7 +625,7 @@ void print_rr_graph_stats() { /* Get the minimum SB mux size */ int num_sb_mux = 0; - short avg_sb_mux_size = 0; + size_t avg_sb_mux_size = 0; for (int inode = 0; inode < num_rr_nodes; ++inode) { /* MUX multiplexers for SBs */ if ( (CHANX == rr_node[inode].type) @@ -640,7 +640,7 @@ void print_rr_graph_stats() { vpr_printf(TIO_MESSAGE_INFO, "Total No. of Switch Block Multiplexer size:%d\n", num_sb_mux); vpr_printf(TIO_MESSAGE_INFO, "Maximum Switch Block Multiplexer size:%d\n", max_sb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "Minimum Switch Block Multiplexer size:%d\n", min_sb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Average Switch Block Multiplexer size:%d\n", avg_sb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Average Switch Block Multiplexer size:%lu\n", avg_sb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); /* Get the maximum SB mux size */ @@ -662,7 +662,7 @@ void print_rr_graph_stats() { /* Get the minimum SB mux size */ int num_cb_mux = 0; - short avg_cb_mux_size = 0; + size_t avg_cb_mux_size = 0; for (int inode = 0; inode < num_rr_nodes; ++inode) { /* MUX multiplexers for SBs */ if (IPIN == rr_node[inode].type) { @@ -675,7 +675,7 @@ void print_rr_graph_stats() { vpr_printf(TIO_MESSAGE_INFO, "Total No. of Connection Block Multiplexer size:%d\n", num_cb_mux); vpr_printf(TIO_MESSAGE_INFO, "Maximum Connection Block Multiplexer size:%d\n", max_cb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "Minimum Connection Block Multiplexer size:%d\n", min_cb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Average Connection Block Multiplexer size:%d\n", avg_cb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Average Connection Block Multiplexer size:%lu\n", avg_cb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 0cca853d8..011eca31a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -51,8 +51,7 @@ void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, t_spice_model* spice_models); static -void init_and_check_sram_inf(t_arch* arch, - t_det_routing_arch* routing_arch); +void init_and_check_sram_inf(t_arch* arch); static t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, @@ -378,8 +377,7 @@ void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, } static -void init_and_check_sram_inf(t_arch* arch, - t_det_routing_arch* routing_arch) { +void init_and_check_sram_inf(t_arch* arch) { /* We have two branches: * 1. SPICE SRAM organization information * 2. Verilog SRAM organization information @@ -511,7 +509,7 @@ void init_check_arch_spice_models(t_arch* arch, } /* Step C: Find SRAM Model*/ - init_and_check_sram_inf(arch, routing_arch); + init_and_check_sram_inf(arch); /* Step D: Find the segment spice_model*/ for (i = 0; i < arch->num_segments; i++) { @@ -689,7 +687,7 @@ void rec_identify_pb_type_phy_mode(t_pb_type* cur_pb_type) { /* Identify physical mode of pb_types in each defined complex block */ static -void init_check_arch_pb_type_idle_and_phy_mode(t_arch* Arch) { +void init_check_arch_pb_type_idle_and_phy_mode() { int itype; for (itype = 0; itype < num_types; itype++) { @@ -1330,7 +1328,7 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, init_check_arch_spice_models(Arch, &(vpr_setup.RoutingArch)); /* Initialize idle mode and physical mode of each pb_type and pb_graph_node */ - init_check_arch_pb_type_idle_and_phy_mode(Arch); + init_check_arch_pb_type_idle_and_phy_mode(); /* Create and initialize a linked list for global ports */ global_ports_head = init_llist_global_ports(Arch->spice);