From 1a1c3885e73bce43b2c0df7e928ca62c4ef6f009 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 13:54:09 -0600 Subject: [PATCH] use k6 n10 in mux designs to speed up CI --- openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf | 4 ++-- .../tasks/mux_design/tree_structure/config/task.conf | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf index 426bb8884..bd770ab87 100644 --- a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf @@ -15,12 +15,12 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf index 9c63bfdbd..ccc293b69 100644 --- a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf @@ -15,12 +15,12 @@ spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif