diff --git a/docs/source/manual/arch_lang/generality.rst b/docs/source/manual/arch_lang/generality.rst index d594ff896..af7719b9a 100644 --- a/docs/source/manual/arch_lang/generality.rst +++ b/docs/source/manual/arch_lang/generality.rst @@ -1,4 +1,4 @@ -.. _generality: +.. _arch_generality: General Hierarchy ----------------- @@ -13,34 +13,49 @@ In the following sub-sections, we will introduce the structures of these XML nod For OpenFPGA using VPR8 ~~~~~~~~~~~~~~~~~~~~~~~ -OpenFPGA uses a separated XML file other than the VPR8 architecture description file. +OpenFPGA uses separated XMLs file other than the VPR8 architecture description file. This is to keep a loose integration to VPR8 so that OpenFPGA can easily integrate any future version of VPR with least engineering effort. However, to implement a physical FPGA, OpenFPGA requires the original VPR XML to include full physical design details. Full syntax can be found in :ref:`addon_vpr_syntax`. -The OpenFPGA architecture description XML file consisting of the following parts: +The OpenFPGA requires two XML files: an architecture description file and a simulation setting description file. - - ```` contains architecture-level information, such as device-level description, circuit-level and architecture annotations to original VPR architecture XML. It consists of the following code blocks +OpenFPGA Architecture Description File +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This file contains device-level and circuit-level details as well as annotations to the original VPR architecture. +It contains a root node called ```` under which architecture-level information, such as device-level description, circuit-level and architecture annotations to original VPR architecture XML are defined. + +It consists of the following code blocks - ```` includes a number of ``circuit_model``, each of which describe a primitive block in FPGA architecture, such as Look-Up Tables and multiplexers. Full syntax can be found in :ref:`circuit_library`. - - ```` includes transistor-level parameters, where users can specify which transistor models are going to be used when building the ``circuit models``. - - ```` includes detailed description on the configuration protocols to be used in FPGA fabric. - - ```` includes annotation on the connection block definition ```` in original VPR XML - - ```` includes annotation on the switch block definition ```` in original VPR XML - - ```` includes annotation on the routing segment definition ```` in original VPR XML - - ```` includes annotation on the inter-tile direct connection definitioin ```` in original VPR XML - - ```` includes annotation on the programmable block architecture ```` in original VPR XML - - - ```` includes all the parameters to be used in generate testbenches in simulation purpose. Full syntax can be found in :ref:`simulation_setting`. - - - ```` defines the clock-related settings in simulation, such as clock frequency and number of clock cycles to be used - - ```` defines universal options available in both HDL and SPICE simulators. This is mainly used by FPGA-SPICE - - ```` defines critical parameters to be used in monte-carlo simulations. This is used by FPGA-SPICE - - ```` defines the parameters used to measure signal slew and delays. This is used by FPGA-SPICE - - ```` defines the parameters used to generate voltage stimuli in testbenches. This is used by FPGA-SPICE + - ```` includes transistor-level parameters, where users can specify which transistor models are going to be used when building the ``circuit models``. Full syntax can be found in :ref:`technology_library`. + - ```` includes detailed description on the configuration protocols to be used in FPGA fabric. Full syntax can be found in :ref:`config_protocol`. + - ```` includes annotation on the connection block definition ```` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`. + - ```` includes annotation on the switch block definition ```` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`. + - ```` includes annotation on the routing segment definition ```` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`. + - ```` includes annotation on the inter-tile direct connection definitioin ```` in original VPR XML. Full syntax can be found in :ref:`direct_interconnect`. + - ```` includes annotation on the programmable block architecture ```` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`. .. note:: ```` will be applied to ``circuit_model`` when running FPGA-SPICE. It will not impact FPGA-Verilog, FPGA-Bitstream, FPGA-SDC. + +OpenFPGA Simulation Setting File +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This file contains parameters required by testbench generators. +It contains a root node ````, under which all the parameters to be used in generate testbenches in simulation purpose are defined. + +It consists of the following code blocks + + - ```` defines the clock-related settings in simulation, such as clock frequency and number of clock cycles to be used. + - ```` defines universal options available in both HDL and SPICE simulators. This is mainly used by :ref:`fpga_spice`. + - ```` defines critical parameters to be used in monte-carlo simulations. This is used by :ref:`fpga_spice`. + - ```` defines the parameters used to measure signal slew and delays. This is used by :ref:`fpga_spice`. + - ```` defines the parameters used to generate voltage stimuli in testbenches. This is used by :ref:`fpga_spice`. + +Full syntax can be found in :ref:`simulation_setting`. + .. note:: the parameters in ```` will be applied to both FPGA-Verilog and FPGA-SPICE simulations diff --git a/docs/source/manual/fpga_spice/index.rst b/docs/source/manual/fpga_spice/index.rst index 4cdffcc0f..b8ce29223 100644 --- a/docs/source/manual/fpga_spice/index.rst +++ b/docs/source/manual/fpga_spice/index.rst @@ -1,11 +1,10 @@ +.. _fpga_spice: + FPGA-SPICE ---------- .. warning:: FPGA-SPICE has not been integrated to VPR8 version yet. Please the following tool guide is for VPR7 version now -.. _fpga_spice: - FPGA-SPICE - .. toctree:: :maxdepth: 2 diff --git a/docs/source/manual/openfpga_shell/openfpga_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands.rst index 6e2f0e490..eb5929861 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands.rst @@ -28,7 +28,7 @@ Setup OpenFPGA .. option:: read_openfpga_arch - Read the XML architecture file required by OpenFPGA + Read the XML file about architecture description (see details in :ref:`arch_generality`) - ``--file`` or ``-f`` Specify the file name @@ -42,6 +42,22 @@ Setup OpenFPGA - ``--verbose`` Show verbose log +.. option:: read_openfpga_simulation_setting + + Read the XML file about simulation settings (see details in :ref:`simulation_setting`) + + - ``--file`` or ``-f`` Specify the file name + + - ``--verbose`` Show verbose log + +.. option:: write_openfpga_simulation_setting + + Write the OpenFPGA XML simulation settings to a file + + - ``--file`` or ``-f`` Specify the file name + + - ``--verbose`` Show verbose log + .. option:: link_openfpga_arch Annotate the OpenFPGA architecture to VPR data base