From 19d4d9a16d6f391dfaa3ebf932887955d60e9f8c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 21:05:26 -0700 Subject: [PATCH] [core] code format --- .../src/fabric/build_top_module_child_tile_instance.cpp | 8 +++++--- openfpga/src/utils/check_tile_annotation.cpp | 9 ++++++--- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 88c0e0731..e8ef67488 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1341,8 +1341,9 @@ static int build_top_module_global_net_for_given_tile_module( return CMD_EXEC_FATAL_ERROR; } grid_pin_start_index = - sub_tile.sub_tile_to_tile_pin_indices[(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + - tile_port.absolute_first_pin_index]; + sub_tile.sub_tile_to_tile_pin_indices + [(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + + tile_port.absolute_first_pin_index]; physical_tile_port = tile_port; break; } @@ -1386,7 +1387,8 @@ static int build_top_module_global_net_for_given_tile_module( generate_tile_module_port_name(grid_instance_name, grid_port_name); ModulePortId tile_grid_port_id = module_manager.find_module_port(tile_module, tile_grid_port_name); - VTR_LOG("Finding global port '%s' from grid '%s'\n", tile_grid_port_name.c_str(), tile_module_name.c_str()); + VTR_LOG("Finding global port '%s' from grid '%s'\n", + tile_grid_port_name.c_str(), tile_module_name.c_str()); VTR_ASSERT(true == module_manager.valid_module_port_id( tile_module, tile_grid_port_id)); diff --git a/openfpga/src/utils/check_tile_annotation.cpp b/openfpga/src/utils/check_tile_annotation.cpp index 68097d2af..929a3b24e 100644 --- a/openfpga/src/utils/check_tile_annotation.cpp +++ b/openfpga/src/utils/check_tile_annotation.cpp @@ -167,7 +167,8 @@ static int check_tile_annotation_conflicts_with_physical_tile( } /* Check if port property matches */ - int grid_pin_index = sub_tile.sub_tile_to_tile_pin_indices[tile_port.absolute_first_pin_index]; + int grid_pin_index = sub_tile.sub_tile_to_tile_pin_indices + [tile_port.absolute_first_pin_index]; if (tile_port.is_clock != tile_annotation.global_port_is_clock(tile_global_port)) { @@ -218,7 +219,8 @@ static int check_tile_annotation_conflicts_with_physical_tile( if (0 == found_matched_physical_tile_port) { VTR_LOGF_ERROR( __FILE__, __LINE__, - "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match " + "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not " + "match " "any physical tile port!\n", required_tile_name.c_str(), required_tile_port.get_name().c_str(), required_tile_port.get_lsb(), required_tile_port.get_msb(), @@ -228,7 +230,8 @@ static int check_tile_annotation_conflicts_with_physical_tile( if (1 < found_matched_physical_tile_port) { VTR_LOGF_ERROR( __FILE__, __LINE__, - "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more than " + "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more " + "than " "1 physical tile port!\n", required_tile_name.c_str(), required_tile_port.get_name().c_str(), required_tile_port.get_lsb(), required_tile_port.get_msb(),