[doc] add references

README.md

@@ -54,6 +54,8 @@ Bibtex:
 @ARTICLE{9098028,  author={Tang, Xifan and Giacomin, Edouard and Chauviere, Baudouin and Alacchi, Aurélien and Gaillardon, Pierre-Emmanuel},  journal={IEEE Micro},   title={OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs},   year={2020},  volume={40},  number={4},  pages={41-48},  doi={10.1109/MM.2020.2995854}}
 ```
 
+A list of related publications can be found [here](https://openfpga.readthedocs.io/en/master/reference/).
+
 ## Contributing to OpenFPGA
 
 Please read the [contributor guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/contributor_guide) if you would like to contribute to OpenFPGA.

docs/source/overview/motivation.rst

@@ -54,7 +54,7 @@ programmable fabric and the configuration peripheral.
 
    OpenFPGA architecture description language enabling fully customizable FPGA architecture and circuit-level implementation
 
-The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
+The technical details can be found in our papers :cite:`XTang_TVLSI_2019` :cite:`XTang_FPL_2019`.
 
 FPGA-Verilog
 ~~~~~~~~~~~~
@@ -73,7 +73,7 @@ FPGA-Verilog is designed to output flexible and standard Verilog netlists, enabl
 
    FPGA-Verilog enabling flexible backend flows
 
-The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
+The technical details can be found in our papers :cite:`XTang_ieeemicro_2020` :cite:`XTang_woset_2020` :cite:`GGore_ispd_2021`
 
 FPGA-SDC
 ~~~~~~~~
@@ -94,7 +94,7 @@ Our flow automatically generates two sets of SDC files.
    FPGA-SDC enabling iterative timing constrained backend flow
 
 
-The technical details can be found in our FPL'19 paper :cite:`XTang_FPL_2019`.
+The technical details can be found in our papers :cite:`XTang_FPL_2019` :cite:`XTang_ieeemicro_2020` :cite:`XTang_woset_2020`.
 
 
 FPGA-Bitstream
@@ -102,7 +102,7 @@ FPGA-Bitstream
 
 EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generators for customized FPGAs. Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow, the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics.
 
-The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
+The technical details can be found in our papers :cite:`XTang_TVLSI_2019` :cite:`XTang_FPL_2019`.
 
 FPGA-SPICE
 ~~~~~~~~~~
@@ -114,4 +114,4 @@ FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA archit
 
 SPICE modeling for FPGA architectures requires detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we are developing an extension on the VPR architectural description language to model the transistor-level circuit designs.
 
-The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
+The technical details can be found in our papers :cite:`XTang_ICCD_2015` :cite:`XTang_TVLSI_2019`.

docs/source/z_reference.bib

@@ -104,3 +104,30 @@ volume={},
 number={},
 doi={10.1109/ICFPT47387.2019.00039},
 pages={247-250},}
+
+@ARTICLE{XTang_ieeemicro_2020,  author={Tang, Xifan and Giacomin, Edouard and Chauviere, Baudouin and Alacchi, Aurélien and Gaillardon, Pierre-Emmanuel},  journal={IEEE Micro},   title={OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs},   year={2020},  volume={40},  number={4},  pages={41-48},  doi={10.1109/MM.2020.2995854}}
+
+@article{XTang_woset_2020,
+  title={OpenFPGA: Towards Automated Prototyping for Versatile FPGAs},
+  author={Tang, Xifan and Gore, Ganesh and Giacomin, Edouard and Alacchi, Aur{\'e}lien and Chauviere, Baudouin and Gaillardon, Pierre-Emmanuel},
+  journal={Workshop on Open-Source EDA Technology},
+  year={2020}
+}
+
+@inproceedings{GGore_ispd_2021,
+author = {Gore, Ganesh and Tang, Xifan and Gaillardon, Pierre-Emmanuel},
+title = {A Scalable and Robust Hierarchical Floorplanning to Enable 24-Hour Prototyping for 100k-LUT FPGAs},
+year = {2021},
+isbn = {9781450383004},
+publisher = {Association for Computing Machinery},
+address = {New York, NY, USA},
+url = {https://doi.org/10.1145/3439706.3447047},
+doi = {10.1145/3439706.3447047},
+abstract = {Physical design for Field Programmable Gate Array (FPGA) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the FPGA design. The growing number of FPGA applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT FPGA layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern FPGA fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT FPGA fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs FPGA device.},
+booktitle = {Proceedings of the 2021 International Symposium on Physical Design},
+pages = {135–142},
+numpages = {8},
+keywords = {reconfigurable computing, hierarchical design, physical design, fpga design},
+location = {Virtual Event, USA},
+series = {ISPD '21}
+}