From 198882da8962076ee5bcafec378da5da5917457d Mon Sep 17 00:00:00 2001 From: bbleaptrot <35536624+bbleaptrot@users.noreply.github.com> Date: Mon, 12 Apr 2021 14:20:40 -0600 Subject: [PATCH] Update link to From Verilog to Verification --- .../tutorials/arch_modeling/open_cell_libraries_tutorial.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst b/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst index d3e7e37d5..86e8ccaf2 100644 --- a/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst +++ b/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst @@ -291,7 +291,7 @@ Replace all the text within ``iverilog_output.txt`` with the following: iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb -I ${OPENFPGA_PATH}/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2 -We can now manually rerun IVerilog, a tutorial on manually running IVerilog can be found at our :ref:`verilog2verification` tutorial. From the root +We can now manually rerun IVerilog, a tutorial on manually running IVerilog can be found at our `From Verilog to Verification `_ tutorial. From the root directory, run the following commands: .. code-block:: bash