Indent code-blocks
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@ -16,7 +16,7 @@ Go to line 187 and replace it with:
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.. code-block:: XML
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<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="">
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<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="">
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Motivation
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~~~~~~~~~~
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@ -58,52 +58,52 @@ To implement our own ADDF module, we need to remove all other module definitions
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.. code-block:: Verilog
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Template for user-defined Verilog modules
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Fri Mar 19 10:05:32 2021
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Template for user-defined Verilog modules
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Fri Mar 19 10:05:32 2021
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// ----- Template Verilog module for ADDF -----
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//----- Default net type -----
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`default_nettype none
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// ----- Template Verilog module for ADDF -----
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for ADDF -----
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module ADDF(A,
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B,
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CI,
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SUM,
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CO);
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//----- INPUT PORTS -----
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input [0:0] A;
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//----- INPUT PORTS -----
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input [0:0] B;
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//----- INPUT PORTS -----
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input [0:0] CI;
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//----- OUTPUT PORTS -----
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output [0:0] SUM;
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//----- OUTPUT PORTS -----
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output [0:0] CO;
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// ----- Verilog module for ADDF -----
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module ADDF(A,
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B,
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CI,
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SUM,
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CO);
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//----- INPUT PORTS -----
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input [0:0] A;
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//----- INPUT PORTS -----
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input [0:0] B;
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//----- INPUT PORTS -----
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input [0:0] CI;
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//----- OUTPUT PORTS -----
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output [0:0] SUM;
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//----- OUTPUT PORTS -----
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output [0:0] CO;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- Internal logic should start here -----
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assign SUM = A ^ B ^ CI;
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assign CO = (A & B) | (A & CI) | (B & CI);
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// ----- Internal logic should end here -----
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endmodule
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// ----- END Verilog module for ADDF -----
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// ----- Internal logic should start here -----
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assign SUM = A ^ B ^ CI;
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assign CO = (A & B) | (A & CI) | (B & CI);
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// ----- Internal logic should end here -----
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endmodule
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// ----- END Verilog module for ADDF -----
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We can now link this ``user_defined_templates.v`` into ``k6_frac_N10_adder_chain_40nm_openfpga.xml``.
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