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OpenFPGA
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[test] update W

This commit is contained in:
tangxifan 2024-07-10 10:01:31 -07:00
parent 81fe722d98
commit 191a3d1c5e
3 changed files with 3 additions and 3 deletions
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2
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
openfpga_vpr_device_layout=2x2 openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40 openfpga_vpr_route_chan_width=60
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options=--disable_unused_spines openfpga_route_clock_options=--disable_unused_spines

2
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
openfpga_vpr_device_layout=2x2 openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40 openfpga_vpr_route_chan_width=60
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options= openfpga_route_clock_options=

2
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf
View File

@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
openfpga_vpr_device_layout=2x2 openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40 openfpga_vpr_route_chan_width=60
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options= openfpga_route_clock_options=