diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst index d764ced67..56032a5e0 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst @@ -24,6 +24,14 @@ Repack's functionality are in the following aspects: See details in :ref:`file_formats_repack_design_constraints`. .. warning:: Design constraints are designed to help repacker to identify which clock net to be mapped to which pin, so that multi-clock benchmarks can be correctly implemented, in the case that VPR may not have sufficient vision on clock net mapping. **Try not to use design constraints to remap any other types of nets!!!** + + .. option:: --ignore_global_nets_on_pins + + Specify the mapping results of global nets should be ignored on which pins of a ``pb_type``. For example, ``--ignore_global_nets_on_pins clb.I[0:11]``. Once specified, the mapping results on the pins for all the global nets, such as clock, reset *etc.*, are ignored. Routing traces will be appeneded to other pins where the same global nets are mapped to. + + .. note:: This option is designed for global nets which are applied to both data path and global networks. For example, a reset signal is mapped to both a LUT input and the reset pin of a FF. Suggest not to use the option in other purposes! + + .. warning:: Users must specify the size/width of the pin. Currently, OpenFPGA cannot infer the pin size from the architecture!!! .. option:: --verbose diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp index 4f633b5b4..e3bb98b94 100644 --- a/openfpga/src/base/openfpga_bitstream_command.cpp +++ b/openfpga/src/base/openfpga_bitstream_command.cpp @@ -21,9 +21,15 @@ ShellCommandId add_openfpga_repack_command(openfpga::Shell& she const ShellCommandClassId& cmd_class_id, const std::vector& dependent_cmds) { Command shell_cmd("repack"); + /* Add an option '--design_constraints' */ CommandOptionId opt_design_constraints = shell_cmd.add_option("design_constraints", false, "file path to the design constraints"); shell_cmd.set_option_require_value(opt_design_constraints, openfpga::OPT_STRING); + + /* Add an option '--ignore_global_nets_on_pins' */ + CommandOptionId opt_ignore_global_nets = shell_cmd.add_option("ignore_global_nets_on_pins", false, "Specify the pins where global nets will be ignored. Routing traces are merged to other pins"); + shell_cmd.set_option_require_value(opt_ignore_global_nets, openfpga::OPT_STRING); + /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Enable verbose output"); diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp index 17bba43a7..050aba312 100644 --- a/openfpga/src/base/openfpga_repack.cpp +++ b/openfpga/src/base/openfpga_repack.cpp @@ -30,6 +30,7 @@ int repack(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_design_constraints = cmd.option("design_constraints"); + CommandOptionId opt_ignore_global_nets = cmd.option("ignore_global_nets_on_pins"); CommandOptionId opt_verbose = cmd.option("verbose"); /* Load design constraints from file */ @@ -40,22 +41,32 @@ int repack(OpenfpgaContext& openfpga_ctx, repack_design_constraints = read_xml_repack_design_constraints(dc_fname.c_str()); } + /* Setup repacker options */ + RepackOption options; + options.set_design_constraints(repack_design_constraints); + options.set_ignore_global_nets_on_pins(cmd_context.option_value(cmd, opt_ignore_global_nets)); + options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); + + if (!options.valid()) { + VTR_LOG("Detected errors when parsing options!\n"); + return CMD_EXEC_FATAL_ERROR; + } + pack_physical_pbs(g_vpr_ctx.device(), g_vpr_ctx.atom(), g_vpr_ctx.clustering(), openfpga_ctx.mutable_vpr_device_annotation(), openfpga_ctx.mutable_vpr_clustering_annotation(), openfpga_ctx.vpr_bitstream_annotation(), - repack_design_constraints, openfpga_ctx.arch().circuit_lib, - cmd_context.option_enable(cmd, opt_verbose)); + options); build_physical_lut_truth_tables(openfpga_ctx.mutable_vpr_clustering_annotation(), g_vpr_ctx.atom(), g_vpr_ctx.clustering(), openfpga_ctx.vpr_device_annotation(), openfpga_ctx.arch().circuit_lib, - cmd_context.option_enable(cmd, opt_verbose)); + options.verbose_output()); /* TODO: should identify the error code from internal function execution */ return CMD_EXEC_SUCCESS; diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 7538c675a..97cade1f7 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -388,10 +388,11 @@ void add_lb_router_nets(LbRouter& lb_router, const VprDeviceAnnotation& device_annotation, const ClusteringContext& clustering_ctx, const VprClusteringAnnotation& clustering_annotation, - const RepackDesignConstraints& design_constraints, const ClusterBlockId& block_id, - const bool& verbose) { + const RepackOption& options) { size_t net_counter = 0; + bool verbose = options.verbose_output(); + RepackDesignConstraints design_constraints = options.design_constraints(); /* Two spots to find source nodes for each nets * - nets that appear in the inputs of a clustered block @@ -437,6 +438,54 @@ void add_lb_router_nets(LbRouter& lb_router, pb_pin_mapped_nets[pb_pin] = atom_net_id; } + /* Cache the sink nodes/routing traces for the global nets which is specifed to be ignored on given pins */ + std::map> ignored_global_net_sinks; + std::map ignored_atom_nets; + for (int j = 0; j < lb_type->pb_type->num_pins; j++) { + /* Get the source pb_graph pin and find the rr_node in logical block routing resource graph */ + const t_pb_graph_pin* source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, j); + VTR_ASSERT(source_pb_pin->parent_node == pb->pb_graph_node); + + /* Bypass output pins */ + if (OUT_PORT == source_pb_pin->port->type) { + continue; + } + + /* Find the net mapped to this pin in clustering results*/ + ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(block_id, j); + /* Get the actual net id because it may be renamed during routing */ + if (true == clustering_annotation.is_net_renamed(block_id, j)) { + cluster_net_id = clustering_annotation.net(block_id, j); + } + + /* Bypass unmapped pins */ + if (ClusterNetId::INVALID() == cluster_net_id) { + continue; + } + + /* Only for global net which should be ignored, cache the sink nodes */ + BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); + if ( (clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id)) + && (clustering_ctx.clb_nlist.net_is_global(cluster_net_id)) + && (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), curr_pin))) { + /* Find the net mapped to this pin in clustering results*/ + AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; + + std::vector pb_route_indices = find_pb_route_by_atom_net(pb, source_pb_pin, atom_net_id); + VTR_ASSERT(1 == pb_route_indices.size()); + int pb_route_index = pb_route_indices[0]; + t_pb_graph_pin* packing_source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, pb_route_index); + VTR_ASSERT(nullptr != packing_source_pb_pin); + + /* Find all the sink pins in the pb_route, we walk through the input pins and find the pin */ + std::vector sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index); + std::vector sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation); + VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size()); + ignored_global_net_sinks[atom_net_id].insert(ignored_global_net_sinks[atom_net_id].end(), sink_lb_rr_nodes.begin(), sink_lb_rr_nodes.end()); + ignored_atom_nets[atom_net_id] = true; + } + } + /* Cache all the source nodes and sinks node for each net * net_terminal[net][0] is the list of source nodes * net_terminal[net][1] is the list of sink nodes @@ -460,6 +509,12 @@ void add_lb_router_nets(LbRouter& lb_router, /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; + BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); + if ( (ignored_atom_nets[atom_net_id]) + && (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), curr_pin))) { + continue; + } + /* Check if the net information is constrained or not */ std::string constrained_net_name = design_constraints.find_constrained_pin_net(std::string(lb_type->pb_type->name), BasicPort(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number)); @@ -573,6 +628,10 @@ void add_lb_router_nets(LbRouter& lb_router, sink_pb_pin->to_string().c_str()); } + /* Append sink nodes from ignored global net cache */ + sink_lb_rr_nodes.insert(sink_lb_rr_nodes.end(), ignored_global_net_sinks[atom_net_id_to_route].begin(), ignored_global_net_sinks[atom_net_id_to_route].end()); + VTR_LOGV(verbose, "Append %ld sinks from the routing traces of ignored global nets\n", ignored_global_net_sinks[atom_net_id_to_route].size()); + /* Add the net */ add_lb_router_net_to_route(lb_router, lb_rr_graph, std::vector(1, source_lb_rr_node), @@ -671,13 +730,13 @@ void repack_cluster(const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, const VprBitstreamAnnotation& bitstream_annotation, - const RepackDesignConstraints& design_constraints, const ClusterBlockId& block_id, - const bool& verbose) { + const RepackOption& options) { /* Get the pb graph that current clustered block is mapped to */ t_logical_block_type_ptr lb_type = clustering_ctx.clb_nlist.block_type(block_id); t_pb_graph_node* pb_graph_head = lb_type->pb_graph_head; VTR_ASSERT(nullptr != pb_graph_head); + bool verbose = options.verbose_output(); /* We should get a non-empty graph */ const LbRRGraph& lb_rr_graph = device_annotation.physical_lb_rr_graph(pb_graph_head); @@ -693,8 +752,7 @@ void repack_cluster(const AtomContext& atom_ctx, /* Add nets to be routed with source and terminals */ add_lb_router_nets(lb_router, lb_type, lb_rr_graph, atom_ctx, device_annotation, clustering_ctx, const_cast(clustering_annotation), - design_constraints, - block_id, verbose); + block_id, options); /* Initialize the modes to expand routing trees with the physical modes in device annotation * This is a must-do before running the routeri in the purpose of repacking!!! @@ -740,8 +798,7 @@ void repack_clusters(const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, const VprBitstreamAnnotation& bitstream_annotation, - const RepackDesignConstraints& design_constraints, - const bool& verbose) { + const RepackOption& options) { vtr::ScopedStartFinishTimer timer("Repack clustered blocks to physical implementation of logical tile"); for (auto blk_id : clustering_ctx.clb_nlist.blocks()) { @@ -749,8 +806,8 @@ void repack_clusters(const AtomContext& atom_ctx, device_annotation, clustering_annotation, bitstream_annotation, - design_constraints, - blk_id, verbose); + blk_id, + options); } } @@ -808,22 +865,20 @@ void pack_physical_pbs(const DeviceContext& device_ctx, VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, const VprBitstreamAnnotation& bitstream_annotation, - const RepackDesignConstraints& design_constraints, const CircuitLibrary& circuit_lib, - const bool& verbose) { + const RepackOption& options) { /* build the routing resource graph for each logical tile */ build_physical_lb_rr_graphs(device_ctx, device_annotation, - verbose); + options.verbose_output()); /* Call the LbRouter to re-pack each clustered block to physical implementation */ repack_clusters(atom_ctx, clustering_ctx, const_cast(device_annotation), clustering_annotation, bitstream_annotation, - design_constraints, - verbose); + options); /* Annnotate wire LUTs that are ONLY created by repacker!!! * This is a MUST RUN! @@ -833,7 +888,7 @@ void pack_physical_pbs(const DeviceContext& device_ctx, clustering_ctx, device_annotation, circuit_lib, - verbose); + options.verbose_output()); } } /* end namespace openfpga */ diff --git a/openfpga/src/repack/repack.h b/openfpga/src/repack/repack.h index 1a9167bc3..5cb1d8320 100644 --- a/openfpga/src/repack/repack.h +++ b/openfpga/src/repack/repack.h @@ -9,8 +9,8 @@ #include "vpr_clustering_annotation.h" #include "vpr_routing_annotation.h" #include "vpr_bitstream_annotation.h" -#include "repack_design_constraints.h" #include "circuit_library.h" +#include "repack_option.h" /******************************************************************** * Function declaration @@ -25,9 +25,8 @@ void pack_physical_pbs(const DeviceContext& device_ctx, VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, const VprBitstreamAnnotation& bitstream_annotation, - const RepackDesignConstraints& design_constraints, const CircuitLibrary& circuit_lib, - const bool& verbose); + const RepackOption& options); } /* end namespace openfpga */ diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp new file mode 100644 index 000000000..13b3b54ce --- /dev/null +++ b/openfpga/src/repack/repack_option.cpp @@ -0,0 +1,127 @@ +/****************************************************************************** + * Memember functions for data structure RepackOption + ******************************************************************************/ +#include +#include +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "repack_option.h" +#include "openfpga_tokenizer.h" +#include "openfpga_port_parser.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************** + * Public Constructors + *************************************************/ +RepackOption::RepackOption() { + verbose_output_ = false; + num_parse_errors_ = 0; +} + +/************************************************** + * Public Accessors + *************************************************/ +RepackDesignConstraints RepackOption::design_constraints() const { + return design_constraints_; +} + +bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const { + auto result = ignore_global_nets_on_pins_.find(pb_type_name); + if (result == ignore_global_nets_on_pins_.end()) { + /* Not found, return false */ + return false; + } else { + /* If the pin is contained by the ignore list, return true */ + for (BasicPort existing_port : result->second) { + if (existing_port.mergeable(pin) && existing_port.contained(pin)) { + return true; + } + } + } + return false; +} + +bool RepackOption::verbose_output() const { + return verbose_output_; +} + +/****************************************************************************** + * Private Mutators + ******************************************************************************/ +void RepackOption::set_design_constraints(const RepackDesignConstraints& design_constraints) { + design_constraints_ = design_constraints; +} + +void RepackOption::set_ignore_global_nets_on_pins(const std::string& content) { + num_parse_errors_ = 0; + /* Split the content using a tokenizer */ + StringToken tokenizer(content); + std::vector tokens = tokenizer.split(','); + + /* Parse each token */ + for (std::string token : tokens) { + /* Extract the pb_type name and port name */ + StringToken pin_tokenizer(token); + std::vector pin_info = pin_tokenizer.split('.'); + /* Expect two contents, otherwise error out */ + if (pin_info.size() != 2) { + std::string err_msg = std::string("Invalid content '") + token + std::string("' to skip, expect .\n"); + VTR_LOG_ERROR(err_msg.c_str()); + num_parse_errors_++; + continue; + } + std::string pb_type_name = pin_info[0]; + PortParser port_parser(pin_info[1]); + BasicPort curr_port = port_parser.port(); + if (!curr_port.is_valid()) { + std::string err_msg = std::string("Invalid pin definition '") + token + std::string("', expect .[int:int]\n"); + VTR_LOG_ERROR(err_msg.c_str()); + num_parse_errors_++; + continue; + } + + /* Check if the existing port already in the ignore list or not */ + auto result = ignore_global_nets_on_pins_.find(pb_type_name); + if (result == ignore_global_nets_on_pins_.end()) { + /* Not found, push the port */ + ignore_global_nets_on_pins_[pb_type_name].push_back(curr_port); + } else { + /* Already a list of ports. Check one by one. + * - It already contained, do nothing but throw a warning. + * - If we can merge, merge it. + * - Otherwise, create it */ + bool included_by_existing_port = false; + for (BasicPort existing_port : result->second) { + if (existing_port.mergeable(curr_port)) { + if (!existing_port.contained(curr_port)) { + result->second.push_back(curr_port); + included_by_existing_port = true; + break; + } else { + std::string warn_msg = std::string("Pin definition '") + token + std::string("' is already included by other pin\n"); + VTR_LOG_WARN(warn_msg.c_str()); + } + } + } + if (!included_by_existing_port) { + result->second.push_back(curr_port); + } + } + } +} + +void RepackOption::set_verbose_output(const bool& enabled) { + verbose_output_ = enabled; +} + +bool RepackOption::valid() const { + if (num_parse_errors_) { + return false; + } + return true; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/repack/repack_option.h b/openfpga/src/repack/repack_option.h new file mode 100644 index 000000000..a626dc714 --- /dev/null +++ b/openfpga/src/repack/repack_option.h @@ -0,0 +1,52 @@ +#ifndef REPACK_OPTION_H +#define REPACK_OPTION_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +#include +#include +#include "repack_design_constraints.h" + +/* Begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Options for RRGSB writer + *******************************************************************/ +class RepackOption { + public: /* Public constructor */ + /* Set default options */ + RepackOption(); + public: /* Public accessors */ + RepackDesignConstraints design_constraints() const; + /* Identify if a pin should ignore all the global nets */ + bool is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const; + bool verbose_output() const; + public: /* Public mutators */ + void set_design_constraints(const RepackDesignConstraints& design_constraints); + void set_ignore_global_nets_on_pins(const std::string& content); + void set_verbose_output(const bool& enabled); + public: /* Public validators */ + /* Check if the following internal data is valid or not: + * - no parsing errors + */ + bool valid() const; + private: /* Internal Data */ + RepackDesignConstraints design_constraints_; + /* The pin information on which global nets should be mapped to: [pb_type_name][0..num_ports] + * For example: + * - clb.I[0:1], clb.I[5:6] -> ["clb"][BasicPort(I, 0, 1), BasicPort(I, 5, 6)] + * - clb.I[0:1], clb.I[2:6] -> ["clb"][BasicPort(I, 0, 6)] + */ + std::map> ignore_global_nets_on_pins_; + + bool verbose_output_; + + /* A flag to indicate if the data parse is invalid or not */ + int num_parse_errors_; +}; + +} /* End namespace openfpga*/ + +#endif diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v new file mode 100644 index 000000000..193e02073 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v @@ -0,0 +1,26 @@ +///////////////////////////////////////// +// Functionality: A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_on_lut(a, b, q, out, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b; +output reg q; +output wire out; + +always @(posedge rst or posedge clk) begin + if (rst) begin + q <= 0; + end else begin + q <= a; + end +end + +assign out = b & ~rst; + +endmodule diff --git a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga new file mode 100644 index 000000000..707371a80 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --ignore_global_nets_on_pins clb.I[0:11] #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index c6bc65147..617b6705b 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -129,6 +129,8 @@ echo -e "Testing K4N5 with pattern based local routing"; run-task basic_tests/k4_series/k4n5_pattern_local_routing $@ echo -e "Testing K4N4 with custom I/O location syntax"; run-task basic_tests/k4_series/k4n4_custom_io_loc $@ +echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; +run-task basic_tests/k4_series/k4n4_rstOnLut $@ echo -e "Testing different tile organizations"; echo -e "Testing tiles with pins only on top and left sides"; diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/pin_constraints_reset.xml new file mode 100644 index 000000000..317f88671 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf new file mode 100644 index 000000000..ba2269805 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index c0286df54..6ffe9130a 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -22,6 +22,7 @@ Please reveal the following architecture features in the names to help quickly s - reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax +- rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture - : The technology node which the delay numbers are extracted from. - TileOrgz: How tile is organized. * Top-left (Tl): the pins of a tile are placed on the top side and left side only diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml new file mode 100644 index 000000000..84dda3a1c --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml @@ -0,0 +1,627 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +