diff --git a/.travis/regression.sh b/.travis/regression.sh
index da8431965..5d9be167d 100755
--- a/.travis/regression.sh
+++ b/.travis/regression.sh
@@ -11,12 +11,12 @@ compiled_file="compiled_$benchmark"
tb_formal_postfix="_top_formal_verification_random_tb"
verilog_output_dirname="${benchmark}_Verilog"
log_file="${benchmark}_sim.log"
+new_reg_sh="my_regression.sh"
cd $fpga_flow_scripts
-perl rewrite_path_in_file.pl -i $vpr_path/regression_verilog.sh
-perl rewrite_path_in_file.pl -i $vpr_path/VerilogNetlists/ff.v
+perl rewrite_path_in_file.pl -i $vpr_path/regression_verilog.sh -o $vpr_path/$new_reg_sh
cd $my_pwd
@@ -28,7 +28,7 @@ rm -f $log_file
rm -f $compiled_file
# Start the script -> run the fpga generation -> run the simulation -> check the log file
-source regression_verilog.sh
+source $new_reg_sh
iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
vvp $compiled_file -j 16 >> $log_file
diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
index b7630261f..a56d6b3cb 100644
--- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
+++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
@@ -330,7 +330,7 @@
-
+
@@ -372,7 +372,7 @@
-
+
diff --git a/fpga_flow/scripts/arch_rewrite.pl b/fpga_flow/scripts/arch_rewrite.pl
deleted file mode 100644
index 0a3274f50..000000000
--- a/fpga_flow/scripts/arch_rewrite.pl
+++ /dev/null
@@ -1,122 +0,0 @@
-#!usr/bin/perl -w
-use strict;
-use Cwd;
-#use Shell;
-use FileHandle;
-#Use the time
-use Time::gmtime;
-
-my $arch_file;
-my $new_arch_file;
-my $overwrite = "TRUE";
-my $keyword = "OPENFPGAPATHKEYWORD";
-my $folder_top = "OpenFPGA";
-
-sub print_usage()
-{
- print "Usage:\n";
- print " perl [-options]\n";
- print " Options:(Mandatory!)\n";
- print " -i \n";
- print " Options:(Optional)\n";
- print " -o \n";
- print "\n";
- return;
-}
-
-sub opts_read()
-{
- if ($#ARGV == -1){
- print "Error: Not enough input argument!\n";
- &print_usage();
- exit(1);
- } else {
- for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){
- if ("-i" eq $ARGV[$iargv]){
- $arch_file = $ARGV[$iargv+1];
- $iargv++;
- } elsif ("-o" eq $ARGV[$iargv]){
- $new_arch_file = $ARGV[$iargv+1];
- $overwrite = "FALSE";
- $iargv++;
- } else {
- die "WRONG ARGUMENT";
- }
- }
- }
- return;
-}
-
-sub rewriting_required_check($)
-{
- my ($arch) = @_;
- open(F, $arch);
- my @lines=;
- close F;
- my $grep_result = grep ($keyword, @lines);
- if($grep_result >= 1){
- print "Rewrite needed\n";
- return 1;
- } else {
- print "Rewrite NOT needed\n";
- return 0;
- }
-}
-
-sub save_original($)
-{
- my ($template) = @_;
- my $renamed_template = "$template".".bak";
- rename($template, $renamed_template);
-
- return $renamed_template;
-}
-
-sub findPath(){
- my $path;
- my $dir = cwd;
- my @folders = split("/", $dir);
- for(my $count = 0; $count < ($#folders -1); $count++){
- print "path fragment = $folders[$count]\n";
- if($folders[$count] eq ""){
- } else {
- $path = "$path"."/"."$folders[$count]";
- if($folders[$count] eq $folder_top){
- print "$path\n";
- return $path;
- }
- }
- }
- die "ERROR: Script launched from the outside of the $folder_top folder!\n";
-}
-
-sub rewrite_file($ $)
-{
- my ($arch, $template) = @_;
- my $myPath = &findPath();
- open(IN, '<'.$template);
- open(OUT, '>'.$arch);
- while(){
- $_ =~ s/$keyword/$myPath/g;
- print OUT $_;
- }
- return;
-}
-
-sub main()
-{
- &opts_read();
- my $rewrite_needed = &rewriting_required_check($arch_file);
- if($rewrite_needed == 1){
- if($overwrite eq "true"){
- my $template_file = &save_original($arch_file);
- &rewrite_file($arch_file, $template_file);
- } else {
- &rewrite_file($new_arch_file, $arch_file);
- }
- }
- return;
-}
-
-&main();
-exit(1);
diff --git a/fpga_flow/scripts/rewrite_path_in_file.pl b/fpga_flow/scripts/rewrite_path_in_file.pl
index fadedb606..b65868f60 100644
--- a/fpga_flow/scripts/rewrite_path_in_file.pl
+++ b/fpga_flow/scripts/rewrite_path_in_file.pl
@@ -6,8 +6,12 @@ use FileHandle;
#Use the time
use Time::gmtime;
-my $my_file;
+my $arch_file;
+my $new_arch_file;
+my $overwrite = "TRUE";
my $keyword = "OPENFPGAPATHKEYWORD";
+my $default_keyword = "TRUE";
+my $change_to;
my $folder_top = "OpenFPGA";
sub print_usage()
@@ -15,7 +19,10 @@ sub print_usage()
print "Usage:\n";
print " perl [-options]\n";
print " Options:(Mandatory!)\n";
- print " -i \n";
+ print " -i \n";
+ print " Options:(Optional)\n";
+ print " -o \n";
+ print " -k \n";
print "\n";
return;
}
@@ -29,7 +36,17 @@ sub opts_read()
} else {
for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){
if ("-i" eq $ARGV[$iargv]){
- $my_file = $ARGV[$iargv+1];
+ $arch_file = $ARGV[$iargv+1];
+ $iargv++;
+ } elsif ("-o" eq $ARGV[$iargv]){
+ $new_arch_file = $ARGV[$iargv+1];
+ $overwrite = "FALSE";
+ $iargv++;
+ } elsif ("-k" eq $ARGV[$iargv]){
+ $keyword = $ARGV[$iargv+1];
+ $change_to = $ARGV[$iargv+2];
+ $default_keyword = "FALSE";
+ $iargv++;
$iargv++;
} else {
die "WRONG ARGUMENT";
@@ -41,8 +58,8 @@ sub opts_read()
sub rewriting_required_check($)
{
- my ($file) = @_;
- open(F, $file);
+ my ($arch) = @_;
+ open(F, $arch);
my @lines=;
close F;
my $grep_result = grep ($keyword, @lines);
@@ -68,7 +85,7 @@ sub findPath(){
my $path;
my $dir = cwd;
my @folders = split("/", $dir);
- for(my $count = 0; $count < $#folders; $count++){
+ for(my $count = 0; $count < ($#folders -1); $count++){
if($folders[$count] eq ""){
} else {
$path = "$path"."/"."$folders[$count]";
@@ -81,15 +98,23 @@ sub findPath(){
die "ERROR: Script launched from the outside of the $folder_top folder!\n";
}
-sub create_new($ $)
+sub rewrite_file($ $)
{
- my ($file, $template) = @_;
- my $myPath = &findPath();
+ my ($arch, $template) = @_;
open(IN, '<'.$template);
- open(OUT, '>'.$file);
- while(){
- $_ =~ s/$keyword/$myPath/g;
- print OUT $_;
+ open(OUT, '>'.$arch);
+
+ if($default_keyword eq "TRUE"){
+ my $myPath = &findPath();
+ while(){
+ $_ =~ s/$keyword/$myPath/g;
+ print OUT $_;
+ }
+ } else {
+ while(){
+ $_ =~ s/$keyword/$change_to/g;
+ print OUT $_;
+ }
}
return;
}
@@ -97,12 +122,17 @@ sub create_new($ $)
sub main()
{
&opts_read();
- my $rewrite_needed = &rewriting_required_check($my_file);
+ my $rewrite_needed = &rewriting_required_check($arch_file);
if($rewrite_needed == 1){
- my $template_file = &save_original($my_file);
- &create_new($my_file, $template_file);
+ if($overwrite eq "TRUE"){
+ my $template_file = &save_original($arch_file);
+ &rewrite_file($arch_file, $template_file);
+ } else {
+ &rewrite_file($new_arch_file, $arch_file);
+ }
}
return;
}
&main();
+exit(1);
diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff.v b/vpr7_x2p/vpr/VerilogNetlists/ff.v
index c01097048..cf15dc440 100644
--- a/vpr7_x2p/vpr/VerilogNetlists/ff.v
+++ b/vpr7_x2p/vpr/VerilogNetlists/ff.v
@@ -5,7 +5,7 @@
// Coder : Xifan TANG
//-----------------------------------------------------
//------ Include defines: preproc flags -----
-`include "/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v"
+`include "GENERATED_DIR_KEYWORD/SRC/fpga_defines.v"
module static_dff (
/* Global ports go first */
input set, // set input
diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh
index decfa8187..293d9e551 100644
--- a/vpr7_x2p/vpr/regression_verilog.sh
+++ b/vpr7_x2p/vpr/regression_verilog.sh
@@ -4,7 +4,7 @@
# Set variables
# For FPGA-Verilog ONLY
benchmark="test_modes"
-OpenFPGA_path="/research/ece/lnis/USERS/tang/github/OpenFPGA"
+OpenFPGA_path="OPENFPGAPATHKEYWORD"
verilog_output_dirname="${benchmark}_Verilog"
verilog_output_dirpath="$PWD"
tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
@@ -16,20 +16,25 @@ act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
vpr_route_chan_width="200"
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
+ff_path="$vpr_path/VerilogNetlists/ff.v"
+new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
+ff_keyword="GENERATED_DIR_KEYWORD"
+ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
+arch_ff_keyword="FFPATHKEYWORD"
-# Step A: Make sure a clean start
-# Recompile if needed
-#make clean
-#make -j32
# Remove previous designs
rm -rf $verilog_output_dirpath/$verilog_output_dirname
mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
cd $fpga_flow_scripts
-perl arch_rewrite.pl -i $template_arch_xml_file -o $arch_xml_file
+perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
+perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
cd -
# Run VPR
-./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
+./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
+cd $fpga_flow_scripts
+perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
+cd -