From 18acb39fad7595f04d3b82cf8438c97d8b412e22 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 6 Aug 2023 22:12:32 -0700
Subject: [PATCH] [core] fixed a bug where heterogeneous fabric may fail

---
 openfpga/src/fabric/build_memory_modules.cpp  | 32 ++++++++++---------
 .../build_routing_bitstream.cpp               | 16 ++++++----
 2 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index 17d33ccef..80899a04c 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -1384,26 +1384,28 @@ int build_memory_group_module(
       mem_module, child_module, child_instance,
       ModuleManager::e_config_child_type::UNIFIED);
     /* Wire outputs of child module to outputs of parent module */
-    add_module_output_nets_to_memory_group_module(
-      module_manager, mem_module, out_port_name, child_module,
-      mem_out_pin_start_index, child_instance);
-    add_module_output_nets_to_memory_group_module(
-      module_manager, mem_module, outb_port_name, child_module,
-      mem_outb_pin_start_index, child_instance);
-    /* Update pin counter */
     ModulePortId child_out_port_id =
       module_manager.find_module_port(child_module, out_port_name);
-    mem_out_pin_start_index +=
-      module_manager.module_port(child_module, child_out_port_id).get_width();
-
+    if (module_manager.valid_module_port_id(child_module, child_out_port_id)) {
+      add_module_output_nets_to_memory_group_module(
+        module_manager, mem_module, out_port_name, child_module,
+        mem_out_pin_start_index, child_instance);
+      /* Update pin counter */
+      mem_out_pin_start_index +=
+        module_manager.module_port(child_module, child_out_port_id).get_width();
+    }
     ModulePortId child_outb_port_id =
       module_manager.find_module_port(child_module, outb_port_name);
-    mem_outb_pin_start_index +=
-      module_manager.module_port(child_module, child_outb_port_id).get_width();
+    if (module_manager.valid_module_port_id(child_module, child_outb_port_id)) {
+      add_module_output_nets_to_memory_group_module(
+        module_manager, mem_module, outb_port_name, child_module,
+        mem_outb_pin_start_index, child_instance);
+      /* Update pin counter */
+      mem_outb_pin_start_index +=
+        module_manager.module_port(child_module, child_outb_port_id)
+          .get_width();
+    }
   }
-  /* Check pin counter */
-  VTR_ASSERT(mem_out_pin_start_index == num_mems &&
-             mem_outb_pin_start_index == num_mems);
 
   /* Add global ports to the pb_module:
    * This is a much easier job after adding sub modules (instances),
diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
index acb83b4a2..28b79e049 100644
--- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
@@ -102,9 +102,11 @@ static void build_switch_block_mux_bitstream(
              module_manager.module_port(mux_mem_module, mux_mem_out_port_id)
                .get_width());
 
-  VTR_LOGV(verbose, "Added %lu bits to '%s' under '%s'\n", mux_bitstream.size(),
-           bitstream_manager.block_name(mux_mem_block).c_str(),
-           bitstream_manager.block_name(bitstream_manager.block_parent(mux_mem_block)).c_str());
+  VTR_LOGV(
+    verbose, "Added %lu bits to '%s' under '%s'\n", mux_bitstream.size(),
+    bitstream_manager.block_name(mux_mem_block).c_str(),
+    bitstream_manager.block_name(bitstream_manager.block_parent(mux_mem_block))
+      .c_str());
 
   /* Add the bistream to the bitstream manager */
   bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);
@@ -316,9 +318,11 @@ static void build_connection_block_mux_bitstream(
              module_manager.module_port(mux_mem_module, mux_mem_out_port_id)
                .get_width());
 
-  VTR_LOGV(verbose, "Added %lu bits to '%s' under '%s'\n", mux_bitstream.size(),
-           bitstream_manager.block_name(mux_mem_block).c_str(),
-           bitstream_manager.block_name(bitstream_manager.block_parent(mux_mem_block)).c_str());
+  VTR_LOGV(
+    verbose, "Added %lu bits to '%s' under '%s'\n", mux_bitstream.size(),
+    bitstream_manager.block_name(mux_mem_block).c_str(),
+    bitstream_manager.block_name(bitstream_manager.block_parent(mux_mem_block))
+      .c_str());
 
   /* Add the bistream to the bitstream manager */
   bitstream_manager.add_block_bits(mux_mem_block, mux_bitstream);