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bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2

This commit is contained in:
tangxifan 2020-08-19 15:27:30 -06:00
parent 3273f441fe
commit 18735894f9
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
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@ -309,9 +309,9 @@
<!-- Bind the 512x64 single port RAM to the physical implementation --> <!-- Bind the 512x64 single port RAM to the physical implementation -->
<pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000"> <pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
<port name="addr" physical_mode_port="addr1[0:8]"/> <port name="addr" physical_mode_port="addr1[0:8]"/>
<port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="0 -32"/> <port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="-32 -32"/>
<port name="we" physical_mode_port="we1"/> <port name="we" physical_mode_port="we1"/>
<port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="0 -32"/> <port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="-32 -32"/>
<port name="clk" physical_mode_port="clk"/> <port name="clk" physical_mode_port="clk"/>
</pb_type> </pb_type>
<!-- Bind the 1024x32 single port RAM to the physical implementation --> <!-- Bind the 1024x32 single port RAM to the physical implementation -->