From 51fc222d61c4a3425228f1aa131d7e72233d7070 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 10:01:33 -0700 Subject: [PATCH 1/9] [Test] Added a new test case for multi-region QL memory bank --- .../config/task.conf | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank/config/task.conf new file mode 100644 index 000000000..9975aa59d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=--device 2x2 +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From d0fe12faddf38c335ac22ad6c51266a5fa636021 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 10:03:39 -0700 Subject: [PATCH 2/9] [Arch] Add an example OpenFPGA architecture for 2-region QL memory bank --- ...4_N4_40nm_multi_region_qlbank_openfpga.xml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml new file mode 100644 index 000000000..6da1021c5 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7db7e2d8f69c31ab7907c7c5bbdd16c62b97861e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 10:05:27 -0700 Subject: [PATCH 3/9] [Test] Deploy the new test case for multi region QL memory bank to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index c9fd5e378..9e008adc8 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -56,6 +56,7 @@ run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA"; run-task basic_tests/full_testbench/ql_memory_bank --debug --show_thread_logs run-task basic_tests/full_testbench/ql_memory_bank_use_wlr --debug --show_thread_logs +run-task basic_tests/full_testbench/multi_region_ql_memory_bank --debug --show_thread_logs echo -e "Testing testbenches without self checking features"; run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs From ad432e4d95d0ccfe907dddbe82d24890df7d201a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 10:20:40 -0700 Subject: [PATCH 4/9] [Engine] Bug fix in finding the start index of BL/WL for each column/row; --- openfpga/src/utils/memory_bank_utils.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/openfpga/src/utils/memory_bank_utils.cpp b/openfpga/src/utils/memory_bank_utils.cpp index a441813ad..66eb938f3 100644 --- a/openfpga/src/utils/memory_bank_utils.cpp +++ b/openfpga/src/utils/memory_bank_utils.cpp @@ -123,7 +123,12 @@ std::map compute_memory_bank_regional_blwl_start_index_per_tile(con if (iblwl == child_xy_range.first) { blwl_start_index_per_tile[iblwl] = 0; } else { - blwl_start_index_per_tile[iblwl] = num_blwls_per_tile.at(iblwl - 1) + blwl_start_index_per_tile[iblwl - 1]; + auto result = num_blwls_per_tile.find(iblwl - 1); + if (result == num_blwls_per_tile.end()) { + blwl_start_index_per_tile[iblwl] = blwl_start_index_per_tile[iblwl - 1]; + } else { + blwl_start_index_per_tile[iblwl] = result->second + blwl_start_index_per_tile[iblwl - 1]; + } } } return blwl_start_index_per_tile; From 962acda810d92b3a76d495a070a3795591a9ff80 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 11:09:46 -0700 Subject: [PATCH 5/9] [Engine] Bug fix in fabric key generation when computing configurable children --- openfpga/src/base/openfpga_build_fabric.cpp | 1 + openfpga/src/fabric/fabric_key_writer.cpp | 13 +++++++++-- openfpga/src/fabric/fabric_key_writer.h | 1 + .../fpga_bitstream/build_device_bitstream.cpp | 20 +++-------------- openfpga/src/utils/memory_utils.cpp | 22 +++++++++++++++++++ openfpga/src/utils/memory_utils.h | 9 ++++++++ 6 files changed, 47 insertions(+), 19 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp index 08e9ef4f8..2c3f491f9 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric.cpp @@ -132,6 +132,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, VTR_ASSERT(false == fkey_fname.empty()); curr_status = write_fabric_key_to_xml_file(openfpga_ctx.module_graph(), fkey_fname, + openfpga_ctx.arch().config_protocol.type(), cmd_context.option_enable(cmd, opt_verbose)); /* If there is any error, final status cannot be overwritten by a success flag */ if (CMD_EXEC_SUCCESS != curr_status) { diff --git a/openfpga/src/fabric/fabric_key_writer.cpp b/openfpga/src/fabric/fabric_key_writer.cpp index c099d5468..d6bea0527 100644 --- a/openfpga/src/fabric/fabric_key_writer.cpp +++ b/openfpga/src/fabric/fabric_key_writer.cpp @@ -14,6 +14,8 @@ #include "openfpga_naming.h" +#include "memory_utils.h" + #include "fabric_key_writer.h" /* begin namespace openfpga */ @@ -29,6 +31,7 @@ namespace openfpga { ***************************************************************************************/ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, const std::string& fname, + const e_config_protocol_type& config_protocol_type, const bool& verbose) { std::string timer_message = std::string("Write fabric key to XML file '") + fname + std::string("'"); @@ -65,9 +68,15 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, /* Create regions for the keys and load keys by region */ for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { FabricRegionId fabric_region = fabric_key.create_region(); - fabric_key.reserve_region_keys(fabric_region, module_manager.region_configurable_children(top_module, config_region).size()); + + /* Each configuration protocol has some child which should not be in the list. They are typically decoders */ + size_t curr_region_num_config_child = module_manager.region_configurable_children(top_module, config_region).size(); + size_t num_child_to_skip = estimate_num_configurable_children_to_skip_by_config_protocol(config_protocol_type, curr_region_num_config_child); + curr_region_num_config_child -= num_child_to_skip; - for (size_t ichild = 0; ichild < module_manager.region_configurable_children(top_module, config_region).size(); ++ichild) { + fabric_key.reserve_region_keys(fabric_region, curr_region_num_config_child); + + for (size_t ichild = 0; ichild < curr_region_num_config_child; ++ichild) { ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[ichild]; size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[ichild]; vtr::Point child_coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[ichild]; diff --git a/openfpga/src/fabric/fabric_key_writer.h b/openfpga/src/fabric/fabric_key_writer.h index 68e6468b2..3062db15a 100644 --- a/openfpga/src/fabric/fabric_key_writer.h +++ b/openfpga/src/fabric/fabric_key_writer.h @@ -16,6 +16,7 @@ namespace openfpga { int write_fabric_key_to_xml_file(const ModuleManager& module_manager, const std::string& fname, + const e_config_protocol_type& config_protocol_type, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index 0af563914..1c81e2cb3 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -13,6 +13,7 @@ #include "openfpga_naming.h" +#include "memory_utils.h" #include "module_manager_utils.h" #include "build_grid_bitstream.h" @@ -84,23 +85,8 @@ size_t rec_estimate_device_bitstream_num_bits(const ModuleManager& module_manage if (parent_module == top_module) { for (const ConfigRegionId& config_region : module_manager.regions(parent_module)) { size_t curr_region_num_config_child = module_manager.region_configurable_children(parent_module, config_region).size(); - - /* Frame-based configuration protocol will have 1 decoder - * if there are more than 1 configurable children - */ - if ( (CONFIG_MEM_FRAME_BASED == config_protocol_type) - && (2 <= curr_region_num_config_child)) { - curr_region_num_config_child--; - } - - /* Memory configuration protocol will have 2 decoders - * at the top-level - */ - if (CONFIG_MEM_MEMORY_BANK == config_protocol_type - || CONFIG_MEM_QL_MEMORY_BANK == config_protocol_type) { - VTR_ASSERT(2 <= curr_region_num_config_child); - curr_region_num_config_child -= 2; - } + size_t num_child_to_skip = estimate_num_configurable_children_to_skip_by_config_protocol(config_protocol_type, curr_region_num_config_child); + curr_region_num_config_child -= num_child_to_skip; /* Visit all the children in a recursively way */ for (size_t ichild = 0; ichild < curr_region_num_config_child; ++ichild) { diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp index 8e2038b06..e5e44b99c 100644 --- a/openfpga/src/utils/memory_utils.cpp +++ b/openfpga/src/utils/memory_utils.cpp @@ -429,5 +429,27 @@ size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, return sram_port_size; } +size_t estimate_num_configurable_children_to_skip_by_config_protocol(e_config_protocol_type config_protocol_type, + size_t curr_region_num_config_child) { + size_t num_child_to_skip = 0; + /* Frame-based configuration protocol will have 1 decoder + * if there are more than 1 configurable children + */ + if ( (CONFIG_MEM_FRAME_BASED == config_protocol_type) + && (2 <= curr_region_num_config_child)) { + num_child_to_skip = 1; + } + + /* Memory configuration protocol will have 2 decoders + * at the top-level + */ + if (CONFIG_MEM_MEMORY_BANK == config_protocol_type + || CONFIG_MEM_QL_MEMORY_BANK == config_protocol_type) { + VTR_ASSERT(2 <= curr_region_num_config_child); + num_child_to_skip = 2; + } + + return num_child_to_skip; +} } /* end namespace openfpga */ diff --git a/openfpga/src/utils/memory_utils.h b/openfpga/src/utils/memory_utils.h index 88eecf1f3..d34e5f0ce 100644 --- a/openfpga/src/utils/memory_utils.h +++ b/openfpga/src/utils/memory_utils.h @@ -40,6 +40,15 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type, size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits); +/** + * @brief Compute the number of configurable children to be skipped for a given configuration protocol + * For some configuration protocol, the decoders are not counted as configurable children + * (they are included in the list for bitstream generator usage) + * The number of decoders depends on the type of configuration protocol. + */ +size_t estimate_num_configurable_children_to_skip_by_config_protocol(e_config_protocol_type config_protocol_type, + size_t curr_region_num_config_child); + } /* end namespace openfpga */ #endif From 337ed33b689d38e6d7030e3f1205e4f30eebff73 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 11:25:16 -0700 Subject: [PATCH 6/9] [Test] Added a sample fabric key for 2-region QL memory bank --- ..._N4_2x2_multi_region_qlbank_sample_key.xml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbank_sample_key.xml diff --git a/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbank_sample_key.xml b/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbank_sample_key.xml new file mode 100644 index 000000000..94b3b6090 --- /dev/null +++ b/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbank_sample_key.xml @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From abfa3803330a54c46703c69faacb4a601d1f5e13 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 11:27:09 -0700 Subject: [PATCH 7/9] [Test] Added a test case to validate the fabric key of 2-region QL memory bank --- .../config/task.conf | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf new file mode 100644 index 000000000..9ec8f28f7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbank_sample_key.xml +openfpga_vpr_device_layout=auto + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From efed2685850fbc14b2dacbb93af5e2df8b71de1b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 11:30:08 -0700 Subject: [PATCH 8/9] [Test] Deploy new test (for multi-region QL memory bank) to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 9e008adc8..ba0171d2e 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -90,6 +90,7 @@ run-task basic_tests/fabric_key/load_external_key --debug --show_thread_logs run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs run-task basic_tests/fabric_key/load_external_key_qlbank_fpga --debug --show_thread_logs +run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga --debug --show_thread_logs echo -e "Testing K4 series FPGA"; echo -e "Testing K4N4 with facturable LUTs"; From b0aaab9c0373698a3491ac5d7d2e7fa4784469a5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Sep 2021 11:32:13 -0700 Subject: [PATCH 9/9] [Test] Bug fix due to mismatches in device layout between fabric key and VPR settings --- .../load_external_key_multi_region_qlbank_fpga/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf index 9ec8f28f7..97a862f1b 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga/config/task.conf @@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbank_sample_key.xml -openfpga_vpr_device_layout=auto +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml