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[Engine] Update BL/WL port addition for the top-level module in fabric generator

This commit is contained in:
tangxifan 2021-09-24 11:07:58 -07:00
parent 7e27c0caf3
commit 18257b3fa1
3 changed files with 21 additions and 10 deletions
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9
openfpga/src/base/openfpga_naming.cpp
View File

@ -813,6 +813,15 @@ std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib,
return port_name;
}
/*********************************************************************
* Generate the BL/WL port names for the top-level module of an FPGA fabric
* Each BL/WL bus drive a specific configuration region has an unique name
*********************************************************************/
std::string generate_regional_blwl_port_name(const std::string& blwl_port_prefix,
const ConfigRegionId& region_id) {
return blwl_port_prefix + std::string("_config_region_") + std::to_string(size_t(region_id));
}
/*********************************************************************
* Generate the port name for the input bus of a routing multiplexer
* This is very useful in Verilog code generation where the inputs of

4
openfpga/src/base/openfpga_naming.h
View File

@ -16,6 +16,7 @@
#include "circuit_library.h"
#include "device_grid.h"
#include "openfpga_port.h"
#include "module_manager_fwd.h"
/********************************************************************
* Function declaration
@ -183,6 +184,9 @@ std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& port_type);
std::string generate_regional_blwl_port_name(const std::string& blwl_port_prefix,
const ConfigRegionId& region_id);
std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib,
const CircuitModelId& mux_model,
const size_t& mux_size,

18
openfpga/src/fabric/build_top_module_memory_bank.cpp
View File

@ -530,13 +530,12 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager,
break;
}
case BLWL_PROTOCOL_FLATTEN: {
/* BL size is the largest among all the regions */
size_t bl_size = 0;
/* Each region will have independent BLs */
for (const ConfigRegionId& config_region : module_manager.regions(module_id)) {
bl_size = std::max(bl_size, num_config_bits[config_region].first);
}
BasicPort bl_port(std::string(MEMORY_BL_PORT_NAME), bl_size);
size_t bl_size = num_config_bits[config_region].first;
BasicPort bl_port(generate_regional_blwl_port_name(std::string(MEMORY_BL_PORT_NAME), config_region), bl_size);
module_manager.add_port(module_id, bl_port, ModuleManager::MODULE_INPUT_PORT);
}
break;
}
case BLWL_PROTOCOL_SHIFT_REGISTER: {
@ -567,13 +566,12 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager,
break;
}
case BLWL_PROTOCOL_FLATTEN: {
/* WL size is the largest among all the regions */
size_t wl_size = 0;
/* Each region will have independent WLs */
for (const ConfigRegionId& config_region : module_manager.regions(module_id)) {
wl_size = std::max(wl_size, num_config_bits[config_region].first);
}
BasicPort wl_port(std::string(MEMORY_WL_PORT_NAME), wl_size);
size_t wl_size = num_config_bits[config_region].first;
BasicPort wl_port(generate_regional_blwl_port_name(std::string(MEMORY_WL_PORT_NAME), config_region), wl_size);
module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT);
}
break;
}
case BLWL_PROTOCOL_SHIFT_REGISTER: {