[Tool] Add regions to fabric bitstream

openfpga/src/fpga_bitstream/fabric_bitstream.cpp

@@ -18,6 +18,9 @@ FabricBitstream::FabricBitstream() {
   invalid_bit_ids_.clear();
   address_length_ = 0;
   wl_address_length_ = 0;
+
+  num_regions_ = 0;
+  invalid_region_ids_.clear();
 }
 
 /**************************************************
@@ -33,6 +36,23 @@ FabricBitstream::fabric_bit_range FabricBitstream::bits() const {
                          fabric_bit_iterator(FabricBitId(num_bits_), invalid_bit_ids_));
 }
 
+size_t FabricBitstream::num_regions() const {
+  return num_regions_;
+}
+
+/* Find all the configuration bits */
+FabricBitstream::fabric_bit_region_range FabricBitstream::regions() const {
+  return vtr::make_range(fabric_bit_region_iterator(FabricBitRegionId(0), invalid_region_ids_),
+                         fabric_bit_region_iterator(FabricBitRegionId(num_regions_), invalid_region_ids_));
+}
+
+std::vector<FabricBitId> FabricBitstream::region_bits(const FabricBitRegionId& region_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_region_id(region_id));
+
+  return region_bits_[region_id];
+}
+
 /******************************************************************************
  * Public Accessors
  ******************************************************************************/
@@ -134,19 +154,6 @@ void FabricBitstream::set_bit_din(const FabricBitId& bit_id,
   bit_dins_[bit_id] = din;
 }
 
-void FabricBitstream::reverse() {
-  std::reverse(config_bit_ids_.begin(), config_bit_ids_.end());
-
-  if (true == use_address_) {
-    std::reverse(bit_addresses_.begin(), bit_addresses_.end());
-    std::reverse(bit_dins_.begin(), bit_dins_.end());
-
-    if (true == use_wl_address_) {
-      std::reverse(bit_wl_addresses_.begin(), bit_wl_addresses_.end());
-    }
-  }
-}
-
 void FabricBitstream::set_use_address(const bool& enable) {
   /* Add a lock, only can be modified when num bits are zero*/
   if (0 == num_bits_) {
@@ -177,11 +184,38 @@ void FabricBitstream::set_wl_address_length(const size_t& length) {
   }
 }
 
+void FabricBitstream::reserve_regions(const size_t& num_regions) {
+  region_bits_.reserve(num_regions);
+}
+
+void FabricBitstream::reverse() {
+  std::reverse(config_bit_ids_.begin(), config_bit_ids_.end());
+
+  if (true == use_address_) {
+    std::reverse(bit_addresses_.begin(), bit_addresses_.end());
+    std::reverse(bit_dins_.begin(), bit_dins_.end());
+
+    if (true == use_wl_address_) {
+      std::reverse(bit_wl_addresses_.begin(), bit_wl_addresses_.end());
+    }
+  }
+}
+
+void FabricBitstream::reverse_region_bits(const FabricBitRegionId& region_id) {
+  VTR_ASSERT(true == valid_region_id(region_id));
+
+  std::reverse(region_bits_[region_id].begin(), region_bits_[region_id].end());
+}
+
 /******************************************************************************
  * Public Validators
  ******************************************************************************/
-char FabricBitstream::valid_bit_id(const FabricBitId& bit_id) const {
+bool FabricBitstream::valid_bit_id(const FabricBitId& bit_id) const {
   return (size_t(bit_id) < num_bits_);
 }
 
+bool FabricBitstream::valid_region_id(const FabricBitRegionId& region_id) const {
+  return (size_t(region_id) < num_regions_);
+}
+
 } /* end namespace openfpga */

openfpga/src/fpga_bitstream/fabric_bitstream.h

@@ -93,8 +93,10 @@ class FabricBitstream {
     class lazy_id_iterator;
 
     typedef lazy_id_iterator<FabricBitId> fabric_bit_iterator;
+    typedef lazy_id_iterator<FabricBitRegionId> fabric_bit_region_iterator;
 
     typedef vtr::Range<fabric_bit_iterator> fabric_bit_range;
+    typedef vtr::Range<fabric_bit_region_iterator> fabric_bit_region_range;
 
   public: /* Public constructor */
     FabricBitstream();
@@ -104,6 +106,11 @@ class FabricBitstream {
     size_t num_bits() const;
     fabric_bit_range bits() const;
 
+    /* Find all the configuration regions */
+    size_t num_regions() const;
+    fabric_bit_region_range regions() const;
+    std::vector<FabricBitId> region_bits(const FabricBitRegionId& region_id) const;
+
   public:  /* Public Accessors */
     /* Find the configuration bit id in architecture bitstream database */
     ConfigBitId config_bit(const FabricBitId& bit_id) const;
@@ -139,6 +146,12 @@ class FabricBitstream {
     void set_bit_din(const FabricBitId& bit_id,
                      const char& din);
 
+    /* Reserve regions */
+    void reserve_regions(const size_t& num_regions);
+
+    /* Reserve bits by region */
+    void reverse_region_bits(const FabricBitRegionId& region_id);
+
     /* Reverse bit sequence of the fabric bitstream
      * This is required by configuration chain protocol 
      */
@@ -162,9 +175,15 @@ class FabricBitstream {
     void set_wl_address_length(const size_t& length);
 
   public:  /* Public Validators */
-    char valid_bit_id(const FabricBitId& bit_id) const;
+    bool valid_bit_id(const FabricBitId& bit_id) const;
+    bool valid_region_id(const FabricBitRegionId& bit_id) const;
 
   private: /* Internal data */
+    /* Unique id of a region in the Bitstream */
+    size_t num_regions_; 
+    std::unordered_set<FabricBitRegionId> invalid_region_ids_;
+    vtr::vector<FabricBitRegionId, std::vector<FabricBitId>> region_bits_; 
+
     /* Unique id of a bit in the Bitstream */
     size_t num_bits_; 
     std::unordered_set<FabricBitId> invalid_bit_ids_;

openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h

@@ -13,8 +13,10 @@ namespace openfpga {
 
 /* Strong Ids for BitstreamContext */
 struct fabric_bit_id_tag;
+struct fabric_bit_region_id_tag;
 
 typedef vtr::StrongId<fabric_bit_id_tag> FabricBitId;
+typedef vtr::StrongId<fabric_bit_region_id_tag> FabricBitRegionId;
 
 class FabricBitstream;