From 68c459482f8e3be57325c1f9483d41694d11285f Mon Sep 17 00:00:00 2001 From: egiacomin Date: Wed, 17 Jul 2019 12:09:59 -0600 Subject: [PATCH 1/3] Update building.md --- tutorials/building.md | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tutorials/building.md b/tutorials/building.md index 7525493a4..a91448b36 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -1,7 +1,6 @@ # How to build? ## Dependencies - OpenFPGA requires all the following dependencies: - autoconf - automake @@ -39,10 +38,9 @@ OpenFPGA requires all the following dependencies: - qt5-default ## Docker - -If all these dependancies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). To ease customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command: +If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command: - docker run lnis/open_fpga:release
-*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".* +*Warning: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as "-v".* Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands: - docker build . -t open_fpga @@ -50,8 +48,7 @@ Otherwise, a container where you can build OpenFPGA yourself can be created with [*docker download link*](https://www.docker.com/products/docker-desktop) ## Building - -To build the tool you have to go in OpenFPGA folder and do: +To build the tool, go in the OpenFPGA folder and do: - mkdir build && cd build - cmake .. -DCMAKE_BUILD_TYPE=debug - make (*WARNING using docker you cannot use "make -j", errors will happen*) From 0a5546e43c4bed8e67838b13ddfa313678df6218 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 5 Aug 2019 14:06:07 -0600 Subject: [PATCH 2/3] Fully functional --- .../SRC/fpga_x2p/verilog/verilog_decoder.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 8 +-- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 20 +++++--- .../SRC/fpga_x2p/verilog/verilog_routing.c | 8 +-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 50 +++++++++---------- .../verilog/verilog_top_netlist_utils.c | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 31 +++++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 +- 8 files changed, 70 insertions(+), 54 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c index 3cb4f9a5a..4204a24f5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c @@ -372,7 +372,7 @@ void dump_verilog_membank_one_inv_module(FILE* fp, inv_spice_model->name, inv_spice_model->prefix, instance_tag, inv_index); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 5db74a44f..35ac9bf60 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1142,7 +1142,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt); cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print the pin names! Input and output @@ -1278,7 +1278,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in); fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Inputs */ @@ -1873,7 +1873,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } else { if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, - FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), + FALSE)) { + fprintf(fp, ",\n"); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 446897397..fb0a98ef0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -123,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -228,13 +228,17 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, } /* Call the subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model * Disable recursive here ! */ /*if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {*/ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } @@ -535,7 +539,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, formatted_subckt_prefix, cur_pb_type->name); fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ @@ -610,14 +614,18 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, subckt_require_explicit_port_map = TRUE; } /* Call LUT subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* if we have to add global ports when dumping submodules of LUTs * otherwise, the port map here does not match that of submodules * Only dump the global ports belonging to a spice_model * DISABLE recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Connect inputs*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index eb736e27e..14d200038 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -836,7 +836,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1093,7 +1093,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -2975,7 +2975,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3222,7 +3222,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index c66c00f67..f3bf3d585 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -642,7 +642,7 @@ void dump_verilog_cmos_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -760,7 +760,7 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -863,7 +863,7 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -928,7 +928,7 @@ void dump_verilog_rram_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -1264,7 +1264,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map), TRUE)) { fprintf(fp, ",\n"); } if (true == use_explicit_port_map) { @@ -1307,7 +1307,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1361,7 +1361,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, spice_model.lut_intermediate_buffer->spice_model_name, nextlevel, out_idx); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1456,7 +1456,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1495,7 +1495,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1561,7 +1561,7 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, - my_bool_to_boolean(is_explicit_mapping))) { + my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -1715,7 +1715,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.name, mux_size); fprintf(fp, "module %s_mux(\n", spice_model.name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -1797,7 +1797,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1863,7 +1863,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, iport, ipin); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* check */ @@ -1973,7 +1973,7 @@ void dump_verilog_rram_mux_tree_structure(FILE* fp, /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ @@ -2052,7 +2052,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(\n", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* inputs */ @@ -2070,7 +2070,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ @@ -2115,7 +2115,7 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -2199,7 +2199,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, gen_verilog_one_mux_module_name(&spice_model, mux_size)); } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -2255,7 +2255,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2318,7 +2318,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, spice_model.output_buffer->spice_model_name); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2729,7 +2729,7 @@ void dump_verilog_wire_module(FILE* fp, /* Add an output at middle point for connecting CB inputs */ fprintf(fp, "module %s (\n", wire_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "input wire %s, output wire %s, output wire mid_out);\n", @@ -2742,7 +2742,7 @@ void dump_verilog_wire_module(FILE* fp, fprintf(fp, "module %s (\n", wire_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "input wire %s, output wire %s);\n", @@ -2807,7 +2807,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, fprintf(fp, "//-----LUT module, verilog_model_name=%s -----\n", verilog_model->name); fprintf(fp, "module %s (", verilog_model->name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print module port list */ @@ -3058,7 +3058,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_buffer->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -3102,7 +3102,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_inverter->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index fc8e5a206..f3cc2c5b9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -934,7 +934,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp, fprintf(fp, "%s ", cur_direct->spice_model->name); fprintf(fp, "%s_%d_ (", cur_direct->spice_model->prefix, cur_direct->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input: Print the source grid pin */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index f280af78d..84c28c8a3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -852,7 +852,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map) { + boolean require_explicit_port_map, + boolean is_lib_name) { int dumped_port_cnt; boolean dump_comma = FALSE; t_spice_model_port* cur_spice_model_port = NULL; @@ -901,9 +902,13 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, } else { /* Add explicit port mapping if required */ if (TRUE == require_explicit_port_map ) { - fprintf(fp, ".%s(", - cur_spice_model_port->lib_name); - //cur_spice_model_port->prefix); + if (TRUE == is_lib_name) { + fprintf(fp, ".%s(", + cur_spice_model_port->lib_name); + } else { + fprintf(fp, ".%s(", + cur_spice_model_port->prefix); + } } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, @@ -1861,7 +1866,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, @@ -1914,7 +1919,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -1931,7 +1936,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -2027,7 +2032,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_num_sram); /* Input*/ @@ -2067,7 +2072,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -2084,7 +2089,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -3047,7 +3052,7 @@ void dump_verilog_mem_module_port_map(FILE* fp, * Other ports are not accepted!!! */ /* 1. Global ports! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map, TRUE)) { dump_first_comma = TRUE; } @@ -3164,7 +3169,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3212,7 +3217,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, case SPICE_SRAM_STANDALONE: /* SRAM subckts*/ /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_in[%d:%d], ", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 47b780804..50859c949 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -73,7 +73,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map); + boolean require_explicit_port_map, + boolean is_lib_name); int dump_verilog_global_ports(FILE* fp, t_llist* head, boolean dump_port_type, From 0b46adb5efaf13367eb0cd42adfa2d8d60f65328 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 8 Aug 2019 15:17:43 -0600 Subject: [PATCH 3/3] Correction to the explicit Verilog for FPGAs above 2x2 --- .../verilog/verilog_compact_netlist.c | 11 ++++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 38 +++++++++++++++++-- .../SRC/fpga_x2p/verilog/verilog_routing.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 8 ++++ .../SRC/fpga_x2p/verilog/verilog_tcl_utils.c | 4 ++ .../verilog/verilog_top_netlist_utils.c | 4 ++ 6 files changed, 59 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4c0ec145f..c38ba3b3a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -789,14 +789,15 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); + DeviceCoordinator unique_chan_coordinator = unique_mirror.get_side_block_coordinator(side_manager.get_side()); fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + gen_verilog_routing_channel_one_pin_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack), + unique_chan_coordinator.get_x(), unique_chan_coordinator.get_y(), itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack))); } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), @@ -815,6 +816,8 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } @@ -964,6 +967,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 14d200038..30ac68c03 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -313,6 +313,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping) { int height; @@ -360,7 +361,7 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(unique_x, unique_y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -565,6 +566,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, + 0, 0, /* No explicit mapping*/ FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: @@ -667,6 +669,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, + 0, /*Used in more recent version*/ + 0, /*Used in more recent version*/ FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: @@ -767,12 +771,16 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Find grid_x and grid_y */ grid_x = drive_rr_nodes[inode]->xlow; grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print a grid pin */ fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ + FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1029,7 +1037,9 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, false); + grid_x, grid_y, + 0,0,/*No explicit mapping */ + FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1803,6 +1813,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, } /* Dump OPINs of adjacent CLBs */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -1810,6 +1821,8 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ if (FALSE == dump_port_type) { fprintf(fp, ",\n"); @@ -2078,7 +2091,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ + 0,0, /*No explicit mapping */ + TRUE, false); /* Dump the direction of the port ! */ } } @@ -2315,6 +2329,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or } } /* Dump OPINs of adjacent CLBs */ + puts("CHECK4"); + const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -2322,6 +2338,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2524,6 +2542,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, + 0,/*used in more recent version*/ + 0,/*used in more recent version*/ TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2772,6 +2792,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -2849,6 +2870,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3006,6 +3028,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3253,6 +3276,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,/*No explicit mapping*/ + 0,/*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3582,6 +3607,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, + 0,/*No explicit mapping */ + 0,/*No explicit mapping */ TRUE, false); } @@ -3785,6 +3812,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert((1 == side_cnt)||(2 == side_cnt)); side_cnt = 0; + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print the ports of grids*/ /* only check ipin_rr_nodes of cur_cb_info */ for (side = 0; side < cur_cb_info->num_sides; side++) { @@ -3802,6 +3830,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ TRUE, is_explicit_mapping); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index b126300e7..24b805a6b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -14,6 +14,7 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index b70163422..4311c341f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -638,6 +638,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, des_rr_node->xlow, des_rr_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -723,6 +725,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, mirror_ipin_node->xlow, mirror_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -1769,6 +1773,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), ipin_node->xlow, ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } @@ -1827,6 +1833,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index 256f281a9..c3df4ed95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -187,6 +187,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, mirror_node->xlow, mirror_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE,is_explicit_mapping); /* Do not specify direction of port */ break; } @@ -231,6 +233,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, cur_rr_node->xlow, cur_rr_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ break; case CHANX: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index f3cc2c5b9..8e52d6f5a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -686,6 +686,8 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf cur_cb_info.ipin_rr_node_grid_side[side][inode], cur_cb_info.ipin_rr_node[side][inode]->xlow, cur_cb_info.ipin_rr_node[side][inode]->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } @@ -833,6 +835,8 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, cur_sb_info.opin_rr_node_grid_side[side][inode], cur_sb_info.opin_rr_node[side][inode]->xlow, cur_sb_info.opin_rr_node[side][inode]->ylow, + 0, /*Used in a more recent version*/ + 0, /*Used in a more recent version*/ FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); }