From 6ab0f71896a374d67fd1c6e1c530cc49ff36a033 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 14:38:39 -0700 Subject: [PATCH 01/24] [Test] Add an example of repack pin constraints file --- .../global_tile_4clock/config/repack_pin_constraints.xml | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml new file mode 100644 index 000000000..7610359cf --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml @@ -0,0 +1,5 @@ + + + + + From 9154cfdeecab06fc70a7069f6c39aa1bba27f257 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 15:34:01 -0700 Subject: [PATCH 02/24] [Flow] Add comments for the design constraint file --- .../global_tile_4clock/config/repack_pin_constraints.xml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml index 7610359cf..31f0473f3 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml @@ -1,5 +1,14 @@ + + + From 8578c1ecac17008ebd182031fb16b0c7aac5d8bb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 15:35:13 -0700 Subject: [PATCH 03/24] [Flow] Rename the design contraint file syntax --- .../global_tile_4clock/config/repack_pin_constraints.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml index 31f0473f3..ed4a49775 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml @@ -6,9 +6,9 @@ - the clk[2] port of all the clb tiles available in the FPGA fabric - the clk[3] port of all the clb tiles available in the FPGA fabric --> - - - - + + + + From b57dc7b89897d1154c6cee2191df7b4399950ffd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 16:35:13 -0700 Subject: [PATCH 04/24] [Lib] Add repack design constraint library --- .../src/repack_design_constraints.cpp | 127 ++++++++++++++++++ .../src/repack_design_constraints.h | 112 +++++++++++++++ .../src/repack_design_constraints_fwd.h | 22 +++ 3 files changed, 261 insertions(+) create mode 100644 libopenfpga/librepackdc/src/repack_design_constraints.cpp create mode 100644 libopenfpga/librepackdc/src/repack_design_constraints.h create mode 100644 libopenfpga/librepackdc/src/repack_design_constraints_fwd.h diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.cpp b/libopenfpga/librepackdc/src/repack_design_constraints.cpp new file mode 100644 index 000000000..0db2359f7 --- /dev/null +++ b/libopenfpga/librepackdc/src/repack_design_constraints.cpp @@ -0,0 +1,127 @@ +#include + +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "repack_design_constraints.h" + +/************************************************************************ + * Member functions for class RepackDesignConstraints + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +RepackDesignConstraints::RepackDesignConstraints() { + return; +} + +/************************************************************************ + * Public Accessors : aggregates + ***********************************************************************/ +RepackDesignConstraints::repack_design_constraint_range RepackDesignConstraints::design_constraints() const { + return vtr::make_range(repack_design_constraint_ids_.begin(), repack_design_constraint_ids_.end()); +} + +/************************************************************************ + * Public Accessors : Basic data query + ***********************************************************************/ +RepackDesignConstraints::e_design_constraint_type RepackDesignConstraints::type(const RepackDesignConstraintId& repack_design_constraint_id) const { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + return repack_design_constraint_types_[repack_design_constraint_id]; +} + +std::string RepackDesignConstraints::tile(const RepackDesignConstraintId& repack_design_constraint_id) const { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + return repack_design_constraint_tiles_[repack_design_constraint_id]; +} + +vtr::Point RepackDesignConstraints::tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id) const { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + return vtr::Point(repack_design_constraint_tiles_x_[repack_design_constraint_id], + repack_design_constraint_tiles_y_[repack_design_constraint_id]); +} + +BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + return repack_design_constraint_pins_[repack_design_constraint_id]; +} + +std::string RepackDesignConstraints::net(const RepackDesignConstraintId& repack_design_constraint_id) const { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + return repack_design_constraint_nets_[repack_design_constraint_id]; +} + +bool RepackDesignConstraints::empty() const { + return 0 == design_constraint_ids_.size(); +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void RepackDesignConstraints::reserve_design_constraints(const size_t& num_design_constraints) { + repack_design_constraint_ids_.reserve(num_design_constraints); + repack_design_constraint_tile_types_.reserve(num_design_constraints); + repack_design_constraint_tiles_.reserve(num_design_constraints); + repack_design_constraint_tiles_x_.reserve(num_design_constraints); + repack_design_constraint_tiles_y_.reserve(num_design_constraints); + repack_design_constraint_pins_.reserve(num_design_constraints); + repack_design_constraint_nets_.reserve(num_design_constraints); +} + +RepackDesignConstraintId create_design_constraint(const RepackDesignConstraints::e_design_constraint_type& repack_design_constraint_type) { + /* Create a new id */ + RepackDesignConstraintId repack_design_constraint_id = RepackDesignConstraintId(design_constraint_ids_.size()); + + repack_design_constraint_ids_.push_back(repack_design_constraint_id); + repack_design_constraint_types_.push_back(repack_design_constraint_type); + repack_design_constraint_tiles_.emplace_back(); + repack_design_constraint_tiles_x_.push_back(size_t(-1)); + repack_design_constraint_tiles_y_.push_back(size_t(-1)); + repack_design_constraint_tile_pins_.emplace_back(); + repack_design_constraint_tile_nets_.emplace_back(); + + return repack_design_constraint_id; +} + +void RepackDesignConstraints::set_tile(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& tile) { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + repack_design_constraint_tiles_[repack_design_constaint_id] = tile; +} + +void RepackDesignConstraints::set_tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id, + const vtr::Point& tile_coordinate) { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + repack_design_constraint_tiles_x_[repack_design_constaint_id] = tile_coordinate.x(); + repack_design_constraint_tiles_y_[repack_design_constaint_id] = tile_coordinate.y(); +} + +void RepackDesignConstraints::set_pin(const RepackDesignConstraintId& repack_design_constraint_id, + const BasicPort& pin) { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + repack_design_constraint_pins_[repack_design_constaint_id] = pin; +} + +void RepackDesignConstraints::set_net(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& net) { + /* validate the design_constraint_id */ + VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); + repack_design_constraint_nets_[repack_design_constaint_id] = net; +} + +/************************************************************************ + * Internal invalidators/validators + ***********************************************************************/ +/* Validators */ +bool RepackDesignConstraintId::valid_design_constraint_id(const RepackDesignConstraintId& design_constraint_id) const { + return ( size_t(design_constraint_id) < repack_design_constraint_ids_.size() ) && ( design_constraint_id == repack_design_constraint_ids_[design_constraint_id] ); +} diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.h b/libopenfpga/librepackdc/src/repack_design_constraints.h new file mode 100644 index 000000000..9ade39914 --- /dev/null +++ b/libopenfpga/librepackdc/src/repack_design_constraints.h @@ -0,0 +1,112 @@ +#ifndef REPACK_DESIGN_CONSTRAINTS_H +#define REPACK_DESIGN_CONSTRAINTS_H + +/******************************************************************** + * This file include the declaration of repack design constraints + *******************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_vector.h" + +#include "repack_design_constraints_fwd.h" + +/******************************************************************** + * A data structure to describe the design constraints for repacking tools + * This data structure may include a number of design constraints + * each of which may constrain: + * - pin assignment, for instance, force a net to be mapped to specific pin + * + * Typical usage: + * -------------- + * // Create an object of design constraints + * RepackDesignConstraints repack_design_constraints; + * // Add a pin assignment + * RepackDesignConstraintId repack_dc_id = fabric_key.create_design_constraint(RepackDesignConstraints::PIN_ASSIGNMENT); + * + *******************************************************************/ +class RepackDesignConstraints { + public: /* Type of design constraints */ + enum e_design_constraint_type { + PIN_ASSIGNMENT, + NUM_DESIGN_CONSTRAINT_TYPES + }; + public: /* Types */ + typedef vtr::vector::const_iterator repack_design_constraint_iterator; + /* Create range */ + typedef vtr::Range repack_design_constraint_range; + public: /* Constructors */ + RepackDesignConstraints(); + public: /* Accessors: aggregates */ + repack_design_constraint_range design_constraints() const; + public: /* Public Accessors: Basic data query */ + /* Get the type of constraint */ + e_design_constraint_type type(const RepackDesignConstraintId& repack_design_constraint_id) const; + + /* Get the tile name to be constrained */ + std::string tile(const RepackDesignConstraintId& repack_design_constraint_id) const; + + /* Get the tile coordinate to be constrained */ + vtr::Point tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id) const; + + /* Get the pin to be constrained */ + BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const; + + /* Get the net to be constrained */ + std::string net(const RepackDesignConstraintId& repack_design_constraint_id) const; + + /* Check if there are any design constraints */ + bool empty() const; + + public: /* Public Mutators */ + + /* Reserve a number of design constraints to be memory efficent */ + void reserve_design_constraints(const size_t& num_design_constraints); + + /* Add a design constraint to storage */ + RepackDesignConstraintId create_design_constraint(const e_design_constraint_type& repack_design_constraint_type); + + /* Set the tile name to be constrained */ + void set_tile(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& tile); + + /* Set the tile coordinate to be constrained */ + void set_tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id, + const vtr::Point& tile_coordinate); + + /* Set the pin to be constrained */ + void set_pin(const RepackDesignConstraintId& repack_design_constraint_id, + const BasicPort& pin); + + /* Set the net to be constrained */ + void set_net(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& net); + + public: /* Public invalidators/validators */ + bool valid_design_constraint_id(const RepackDesignConstraintId& repack_design_constraint_id) const; + private: /* Internal data */ + /* Unique ids for each design constraint */ + vtr::vector repack_design_constraint_ids_; + + /* Type for each design constraint */ + vtr::vector repack_design_constraint_types_; + + /* Tiles to constraint */ + vtr::vector repack_design_constraint_tiles_; + + /* Coordinates of tiles to constraint + * Avoid using an object but a flatten way to be memory efficient + */ + vtr::vector repack_design_constraint_tiles_x_; + vtr::vector repack_design_constraint_tiles_y_; + + /* Pins to constraint */ + vtr::vector repack_design_constraint_pins_; + + /* Nets to constraint */ + vtr::vector repack_design_constraint_nets_; +}; + +#endif diff --git a/libopenfpga/librepackdc/src/repack_design_constraints_fwd.h b/libopenfpga/librepackdc/src/repack_design_constraints_fwd.h new file mode 100644 index 000000000..9216a30b0 --- /dev/null +++ b/libopenfpga/librepackdc/src/repack_design_constraints_fwd.h @@ -0,0 +1,22 @@ +/************************************************************************ + * A header file for RepackDesignConstraints class, including critical data declaration + * Please include this file only for using any TechnologyLibrary data structure + * Refer to repack_design_constraints.h for more details + ***********************************************************************/ + +/************************************************************************ + * Create strong id for RepackDesignConstraints to avoid illegal type casting + ***********************************************************************/ +#ifndef REPACK_DESIGN_CONSTRAINTS_FWD_H +#define REPACK_DESIGN_CONSTRAINTS_FWD_H + +#include "vtr_strong_id.h" + +struct repack_design_constraint_id_tag; + +typedef vtr::StrongId RepackDesignConstraintId; + +/* Short declaration of class */ +class RepackDesignConstraints; + +#endif From a926c74ae5cb927317f80865909b799e3512ea29 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 16:35:46 -0700 Subject: [PATCH 05/24] [Lib] Add CMake script to compile the repack design constraint library --- libopenfpga/librepackdc/CMakeLists.txt | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 libopenfpga/librepackdc/CMakeLists.txt diff --git a/libopenfpga/librepackdc/CMakeLists.txt b/libopenfpga/librepackdc/CMakeLists.txt new file mode 100644 index 000000000..6cc89c037 --- /dev/null +++ b/libopenfpga/librepackdc/CMakeLists.txt @@ -0,0 +1,34 @@ +cmake_minimum_required(VERSION 3.9) + +project("librepackdc") + +file(GLOB_RECURSE EXEC_SOURCES test/*.cpp) +file(GLOB_RECURSE LIB_SOURCES src/*.cpp) +file(GLOB_RECURSE LIB_HEADERS src/*.h) +files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) + +#Remove test executable from library +list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCES}) + +#Create the library +add_library(librepackdc STATIC + ${LIB_HEADERS} + ${LIB_SOURCES}) +target_include_directories(librepackdc PUBLIC ${LIB_INCLUDE_DIRS}) +set_target_properties(librepackdc PROPERTIES PREFIX "") #Avoid extra 'lib' prefix + +#Specify link-time dependancies +target_link_libraries(librepackdc + libopenfpgautil + libvtrutil + libpugixml + libpugiutil) + +#Create the test executable +foreach(testsourcefile ${EXEC_SOURCES}) + # Use a simple string replace, to cut off .cpp. + get_filename_component(testname ${testsourcefile} NAME_WE) + add_executable(${testname} ${testsourcefile}) + # Make sure the library is linked to each test executable + target_link_libraries(${testname} librepackdc) +endforeach(testsourcefile ${EXEC_SOURCES}) From 8be12b6e82059b6823b284badecf28652cc8f8f4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 16:36:10 -0700 Subject: [PATCH 06/24] [Lib] Add example design constraint file --- .../dc_example/repack_design_constraint_example.xml | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml diff --git a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml new file mode 100644 index 000000000..dbd2a04d1 --- /dev/null +++ b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml @@ -0,0 +1,7 @@ + + + + + + + From f1bfa2ef8cc96436779f7bf0ac5d4a21d3c24374 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 17:03:01 -0700 Subject: [PATCH 07/24] [Lib] Add XML parser for repack design constraints --- .../read_xml_repack_design_constraints.cpp | 94 +++++++++++++++++++ .../src/read_xml_repack_design_constraints.h | 16 ++++ 2 files changed, 110 insertions(+) create mode 100644 libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp create mode 100644 libopenfpga/librepackdc/src/read_xml_repack_design_constraints.h diff --git a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp new file mode 100644 index 000000000..d6c5eb8aa --- /dev/null +++ b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp @@ -0,0 +1,94 @@ +/******************************************************************** + * This file includes the top-level function of this library + * which reads an XML of a fabric key to the associated + * data structures + *******************************************************************/ +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_time.h" + +/* Headers from libopenfpga util library */ +#include "openfpga_port_parser.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "read_xml_util.h" + +#include "read_xml_repack_design_constraints.h" + +/******************************************************************** + * Parse XML codes of a to an object of FabricKey + *******************************************************************/ +static +void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, + const pugiutil::loc_data& loc_data, + RepackDesignConstraints& repack_design_constraints) { + + /* Create a new design constraint in the storage */ + RepackDesignConstraintId design_constraint_id = repack_design_constraints.create_design_constraint(RepackDesignConstraints::PIN_ASSIGNMENT); + + if (false == repack_design_constraints.valid_design_constraint_id(design_constraint_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), + "Fail to create design constraint!\n"); + } + + repack_design_constraints.set_tile(design_constraint_id, + get_attribute(xml_pin_constraint, "tile", loc_data).as_string()); + + repack_design_constraints.set_tile_coordinate(design_constraint_id, + get_attribute(xml_pin_constraint, "x", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1), + get_attribute(xml_pin_constraint, "y", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1)); + + + openfpga::PortParser port_parser(get_attribute(xml_pin_constraint, "pin", loc_data).as_string()); + + repack_design_constraints.set_pin(design_constraint_id, + port_parser.port()); + + repack_design_constraints.set_net(design_constraint_id, + get_attribute(xml_pin_constraint, "net", loc_data).as_string()); +} + +/******************************************************************** + * Parse XML codes about to an object of RepackDesignConstraints + *******************************************************************/ +RepackDesignConstraints read_xml_repack_design_constraints(const char* design_constraint_fname) { + + vtr::ScopedStartFinishTimer timer("Read Repack Design Constraints"); + + RepackDesignConstraints repack_design_constraints; + + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + + try { + loc_data = pugiutil::load_xml(doc, design_constraint_fname); + + pugi::xml_node xml_root = get_single_child(doc, "repack_design_constraint", loc_data); + + size_t num_design_constraintss = std::distance(xml_root.children().begin(), xml_root.children().end()); + /* Reserve memory space for the region */ + fabric_key.reserve_design_constraints(num_design_constraints); + + for (pugi::xml_node xml_design_constraint : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_design_constraint.name() != std::string("pin_constraint")) { + bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint"}); + } + read_xml_pin_constraint(xml_design_constraint, loc_data, repack_design_constraints); + } + } catch (pugiutil::XmlError& e) { + archfpga_throw(design_constraint_fname, e.line(), + "%s", e.what()); + } + + return fabric_key; +} + diff --git a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.h b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.h new file mode 100644 index 000000000..c2d3917b2 --- /dev/null +++ b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.h @@ -0,0 +1,16 @@ +#ifndef READ_XML_REPACK_DESIGN_CONSTRAINTS_H +#define READ_XML_REPACK_DESIGN_CONSTRAINTS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "pugixml_util.hpp" +#include "pugixml.hpp" +#include "repack_design_constraints.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ +RepackDesignConstraints read_xml_repack_design_constraints(const char* design_constraint_fname); + +#endif From 2a7601fb7ee1c1202cba34f9b95f3987301dcc47 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 17:14:51 -0700 Subject: [PATCH 08/24] [Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints --- libopenfpga/librepackdc/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/libopenfpga/librepackdc/CMakeLists.txt b/libopenfpga/librepackdc/CMakeLists.txt index 6cc89c037..d605e0457 100644 --- a/libopenfpga/librepackdc/CMakeLists.txt +++ b/libopenfpga/librepackdc/CMakeLists.txt @@ -20,6 +20,7 @@ set_target_properties(librepackdc PROPERTIES PREFIX "") #Avoid extra 'lib' prefi #Specify link-time dependancies target_link_libraries(librepackdc libopenfpgautil + libarchopenfpga libvtrutil libpugixml libpugiutil) From 03b5bcc24482c3e4ae4b3a8f9a22912364e7ece8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 17:15:31 -0700 Subject: [PATCH 09/24] [Lib] Add XML writer for repack design constraints --- .../write_xml_repack_design_constraints.cpp | 99 +++++++++++++++++++ .../src/write_xml_repack_design_constraints.h | 16 +++ 2 files changed, 115 insertions(+) create mode 100644 libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp create mode 100644 libopenfpga/librepackdc/src/write_xml_repack_design_constraints.h diff --git a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp new file mode 100644 index 000000000..739419bb6 --- /dev/null +++ b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp @@ -0,0 +1,99 @@ +/******************************************************************** + * This file includes functions that outputs a repack design constraint object to XML format + *******************************************************************/ +/* Headers from system goes first */ +#include +#include + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpga util library */ +#include "openfpga_digest.h" + +/* Headers from arch openfpga library */ +#include "write_xml_utils.h" + +/* Headers from fabrickey library */ +#include "write_xml_repack_design_constraints.h" + +/******************************************************************** + * A writer to output a pin constraint to XML format + * + * Return 0 if successful + * Return 1 if there are more serious bugs in the architecture + * Return 2 if fail when creating files + *******************************************************************/ +static +int write_xml_pin_constraint(std::fstream& fp, + const RepackDesignConstraints& repack_design_constraints, + const RepackDesignConstraintId& design_constraint) { + /* Validate the file stream */ + if (false == openfpga::valid_file_stream(fp)) { + return 2; + } + + openfpga::write_tab_to_file(fp, 1); + fp << "" << "\n"; + + return 0; +} + +/******************************************************************** + * A writer to output a repack design constraint object to XML format + * + * Return 0 if successful + * Return 1 if there are more serious bugs in the architecture + * Return 2 if fail when creating files + *******************************************************************/ +int write_xml_repack_design_constraints(const char* fname, + const RepackDesignConstraints& repack_design_constraints) { + + vtr::ScopedStartFinishTimer timer("Write Repack Design Constraints"); + + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + /* Write the root node */ + fp << "" << "\n"; + + int err_code = 0; + + /* Write region by region */ + for (const RepackDesignConstraintId& design_constraint : repack_design_constraints.design_constraints()) { + /* Write constraint by constraint */ + if (RepackDesignConstraints::PIN_ASSIGNMENT == repack_design_constraints.type(design_constraint)) { + err_code = write_xml_pin_constraint(fp, repack_design_constraints, design_constraint); + if (0 != err_code) { + return err_code; + } + } + } + + /* Finish writing the root node */ + fp << "" << "\n"; + + /* Close the file stream */ + fp.close(); + + return err_code; +} diff --git a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.h b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.h new file mode 100644 index 000000000..441799451 --- /dev/null +++ b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.h @@ -0,0 +1,16 @@ +#ifndef WRITE_XML_REPACK_DESIGN_CONSTRAINTS_H +#define WRITE_XML_REPACK_DESIGN_CONSTRAINTS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "repack_design_constraints.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ +int write_xml_repack_design_constraints(const char* fname, + const RepackDesignConstraints& repack_design_constraints); + +#endif From 9d80f1ab39f570f20e3682dded1c007a5fa64b74 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 17:18:42 -0700 Subject: [PATCH 10/24] [Lib] Add test program to the library of repack design constraints --- .../test/test_repack_design_constraints.cpp | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 libopenfpga/librepackdc/test/test_repack_design_constraints.cpp diff --git a/libopenfpga/librepackdc/test/test_repack_design_constraints.cpp b/libopenfpga/librepackdc/test/test_repack_design_constraints.cpp new file mode 100644 index 000000000..00ec04cea --- /dev/null +++ b/libopenfpga/librepackdc/test/test_repack_design_constraints.cpp @@ -0,0 +1,34 @@ +/******************************************************************** + * Unit test functions to validate the correctness of + * 1. parser of data structures + * 2. writer of data structures + *******************************************************************/ +/* Headers from vtrutils */ +#include "vtr_assert.h" +#include "vtr_log.h" + +/* Headers from fabric key */ +#include "read_xml_repack_design_constraints.h" +#include "write_xml_repack_design_constraints.h" + +int main(int argc, const char** argv) { + /* Ensure we have only one or two argument */ + VTR_ASSERT((2 == argc) || (3 == argc)); + + + /* Parse the fabric key from an XML file */ + RepackDesignConstraints design_constraints = read_xml_repack_design_constraints(argv[1]); + VTR_LOG("Read the repack design constraints from an XML file: %s.\n", + argv[1]); + + /* Output the circuit library to an XML file + * This is optional only used when there is a second argument + */ + if (3 <= argc) { + write_xml_repack_design_constraints(argv[2], test_key); + VTR_LOG("Echo the repack design constraints to an XML file: %s.\n", + argv[2]); + } +} + + From ad7a54db1bb5941e8cc55aa0aed3b6dd0150516e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 17:20:59 -0700 Subject: [PATCH 11/24] [Tool] Add repack dc library to compilation --- libopenfpga/CMakeLists.txt | 1 + openfpga/CMakeLists.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/libopenfpga/CMakeLists.txt b/libopenfpga/CMakeLists.txt index 92d25522a..e889f935a 100644 --- a/libopenfpga/CMakeLists.txt +++ b/libopenfpga/CMakeLists.txt @@ -4,4 +4,5 @@ add_subdirectory(libopenfpgashell) add_subdirectory(libarchopenfpga) add_subdirectory(libopenfpgautil) add_subdirectory(libfabrickey) +add_subdirectory(librepackdc) add_subdirectory(libfpgabitstream) diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt index 8bae1ddf0..f6af7afe0 100644 --- a/openfpga/CMakeLists.txt +++ b/openfpga/CMakeLists.txt @@ -23,6 +23,7 @@ target_link_libraries(libopenfpga libopenfpgashell libopenfpgautil libfabrickey + librepackdc libfpgabitstream libini libvtrutil From 67c54c4d3be21ec2b3dac3055f4804ccb6830f89 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 17:34:22 -0700 Subject: [PATCH 12/24] [Lib] Bug fix in the repack design constraint lib --- .../read_xml_repack_design_constraints.cpp | 10 +++---- .../src/repack_design_constraints.cpp | 28 +++++++++---------- .../src/repack_design_constraints.h | 10 +++++-- .../write_xml_repack_design_constraints.cpp | 2 +- 4 files changed, 27 insertions(+), 23 deletions(-) diff --git a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp index d6c5eb8aa..be63de6bc 100644 --- a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp @@ -42,8 +42,8 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, get_attribute(xml_pin_constraint, "tile", loc_data).as_string()); repack_design_constraints.set_tile_coordinate(design_constraint_id, - get_attribute(xml_pin_constraint, "x", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1), - get_attribute(xml_pin_constraint, "y", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1)); + vtr::Point(get_attribute(xml_pin_constraint, "x", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1), + get_attribute(xml_pin_constraint, "y", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1))); openfpga::PortParser port_parser(get_attribute(xml_pin_constraint, "pin", loc_data).as_string()); @@ -73,9 +73,9 @@ RepackDesignConstraints read_xml_repack_design_constraints(const char* design_co pugi::xml_node xml_root = get_single_child(doc, "repack_design_constraint", loc_data); - size_t num_design_constraintss = std::distance(xml_root.children().begin(), xml_root.children().end()); + size_t num_design_constraints = std::distance(xml_root.children().begin(), xml_root.children().end()); /* Reserve memory space for the region */ - fabric_key.reserve_design_constraints(num_design_constraints); + repack_design_constraints.reserve_design_constraints(num_design_constraints); for (pugi::xml_node xml_design_constraint : xml_root.children()) { /* Error out if the XML child has an invalid name! */ @@ -89,6 +89,6 @@ RepackDesignConstraints read_xml_repack_design_constraints(const char* design_co "%s", e.what()); } - return fabric_key; + return repack_design_constraints; } diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.cpp b/libopenfpga/librepackdc/src/repack_design_constraints.cpp index 0db2359f7..ae395bef7 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/repack_design_constraints.cpp @@ -45,7 +45,7 @@ vtr::Point RepackDesignConstraints::tile_coordinate(const RepackDesignCo repack_design_constraint_tiles_y_[repack_design_constraint_id]); } -BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const { +openfpga::BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); return repack_design_constraint_pins_[repack_design_constraint_id]; @@ -58,7 +58,7 @@ std::string RepackDesignConstraints::net(const RepackDesignConstraintId& repack_ } bool RepackDesignConstraints::empty() const { - return 0 == design_constraint_ids_.size(); + return 0 == repack_design_constraint_ids_.size(); } /************************************************************************ @@ -66,7 +66,7 @@ bool RepackDesignConstraints::empty() const { ***********************************************************************/ void RepackDesignConstraints::reserve_design_constraints(const size_t& num_design_constraints) { repack_design_constraint_ids_.reserve(num_design_constraints); - repack_design_constraint_tile_types_.reserve(num_design_constraints); + repack_design_constraint_types_.reserve(num_design_constraints); repack_design_constraint_tiles_.reserve(num_design_constraints); repack_design_constraint_tiles_x_.reserve(num_design_constraints); repack_design_constraint_tiles_y_.reserve(num_design_constraints); @@ -74,17 +74,17 @@ void RepackDesignConstraints::reserve_design_constraints(const size_t& num_desig repack_design_constraint_nets_.reserve(num_design_constraints); } -RepackDesignConstraintId create_design_constraint(const RepackDesignConstraints::e_design_constraint_type& repack_design_constraint_type) { +RepackDesignConstraintId RepackDesignConstraints::create_design_constraint(const RepackDesignConstraints::e_design_constraint_type& repack_design_constraint_type) { /* Create a new id */ - RepackDesignConstraintId repack_design_constraint_id = RepackDesignConstraintId(design_constraint_ids_.size()); + RepackDesignConstraintId repack_design_constraint_id = RepackDesignConstraintId(repack_design_constraint_ids_.size()); repack_design_constraint_ids_.push_back(repack_design_constraint_id); repack_design_constraint_types_.push_back(repack_design_constraint_type); repack_design_constraint_tiles_.emplace_back(); repack_design_constraint_tiles_x_.push_back(size_t(-1)); repack_design_constraint_tiles_y_.push_back(size_t(-1)); - repack_design_constraint_tile_pins_.emplace_back(); - repack_design_constraint_tile_nets_.emplace_back(); + repack_design_constraint_pins_.emplace_back(); + repack_design_constraint_nets_.emplace_back(); return repack_design_constraint_id; } @@ -93,35 +93,35 @@ void RepackDesignConstraints::set_tile(const RepackDesignConstraintId& repack_de const std::string& tile) { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - repack_design_constraint_tiles_[repack_design_constaint_id] = tile; + repack_design_constraint_tiles_[repack_design_constraint_id] = tile; } void RepackDesignConstraints::set_tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id, const vtr::Point& tile_coordinate) { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - repack_design_constraint_tiles_x_[repack_design_constaint_id] = tile_coordinate.x(); - repack_design_constraint_tiles_y_[repack_design_constaint_id] = tile_coordinate.y(); + repack_design_constraint_tiles_x_[repack_design_constraint_id] = tile_coordinate.x(); + repack_design_constraint_tiles_y_[repack_design_constraint_id] = tile_coordinate.y(); } void RepackDesignConstraints::set_pin(const RepackDesignConstraintId& repack_design_constraint_id, - const BasicPort& pin) { + const openfpga::BasicPort& pin) { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - repack_design_constraint_pins_[repack_design_constaint_id] = pin; + repack_design_constraint_pins_[repack_design_constraint_id] = pin; } void RepackDesignConstraints::set_net(const RepackDesignConstraintId& repack_design_constraint_id, const std::string& net) { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - repack_design_constraint_nets_[repack_design_constaint_id] = net; + repack_design_constraint_nets_[repack_design_constraint_id] = net; } /************************************************************************ * Internal invalidators/validators ***********************************************************************/ /* Validators */ -bool RepackDesignConstraintId::valid_design_constraint_id(const RepackDesignConstraintId& design_constraint_id) const { +bool RepackDesignConstraints::valid_design_constraint_id(const RepackDesignConstraintId& design_constraint_id) const { return ( size_t(design_constraint_id) < repack_design_constraint_ids_.size() ) && ( design_constraint_id == repack_design_constraint_ids_[design_constraint_id] ); } diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.h b/libopenfpga/librepackdc/src/repack_design_constraints.h index 9ade39914..e29fc228b 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.h +++ b/libopenfpga/librepackdc/src/repack_design_constraints.h @@ -10,6 +10,10 @@ /* Headers from vtrutil library */ #include "vtr_vector.h" +#include "vtr_geometry.h" + +/* Headers from openfpgautil library */ +#include "openfpga_port.h" #include "repack_design_constraints_fwd.h" @@ -52,7 +56,7 @@ class RepackDesignConstraints { vtr::Point tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id) const; /* Get the pin to be constrained */ - BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const; + openfpga::BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const; /* Get the net to be constrained */ std::string net(const RepackDesignConstraintId& repack_design_constraint_id) const; @@ -78,7 +82,7 @@ class RepackDesignConstraints { /* Set the pin to be constrained */ void set_pin(const RepackDesignConstraintId& repack_design_constraint_id, - const BasicPort& pin); + const openfpga::BasicPort& pin); /* Set the net to be constrained */ void set_net(const RepackDesignConstraintId& repack_design_constraint_id, @@ -103,7 +107,7 @@ class RepackDesignConstraints { vtr::vector repack_design_constraint_tiles_y_; /* Pins to constraint */ - vtr::vector repack_design_constraint_pins_; + vtr::vector repack_design_constraint_pins_; /* Nets to constraint */ vtr::vector repack_design_constraint_nets_; diff --git a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp index 739419bb6..f044d24d8 100644 --- a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp @@ -45,7 +45,7 @@ int write_xml_pin_constraint(std::fstream& fp, write_xml_attribute(fp, "tile", repack_design_constraints.tile(design_constraint).c_str()); write_xml_attribute(fp, "x", repack_design_constraints.tile_coordinate(design_constraint).x()); write_xml_attribute(fp, "y", repack_design_constraints.tile_coordinate(design_constraint).y()); - write_xml_attribute(fp, "pin", generate_xml_port_name(repack_design_constraints.net(design_constraint)).c_str()); + write_xml_attribute(fp, "pin", generate_xml_port_name(repack_design_constraints.pin(design_constraint)).c_str()); write_xml_attribute(fp, "net", repack_design_constraints.net(design_constraint).c_str()); fp << "/>" << "\n"; From 706e84bb627f831de77978546a1ef9a0dcd4ac4d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 18:15:56 -0700 Subject: [PATCH 13/24] [Lib] Bug fix in testing program --- libopenfpga/librepackdc/test/test_repack_design_constraints.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libopenfpga/librepackdc/test/test_repack_design_constraints.cpp b/libopenfpga/librepackdc/test/test_repack_design_constraints.cpp index 00ec04cea..78a1314ef 100644 --- a/libopenfpga/librepackdc/test/test_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/test/test_repack_design_constraints.cpp @@ -25,7 +25,7 @@ int main(int argc, const char** argv) { * This is optional only used when there is a second argument */ if (3 <= argc) { - write_xml_repack_design_constraints(argv[2], test_key); + write_xml_repack_design_constraints(argv[2], design_constraints); VTR_LOG("Echo the repack design constraints to an XML file: %s.\n", argv[2]); } From fa675173493a7ff153842f578ec86e600a2b863b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 18:49:34 -0700 Subject: [PATCH 14/24] [Tool] Add repack design constraints to openfpga command 'repack' --- openfpga/src/base/openfpga_bitstream_command.cpp | 3 +++ openfpga/src/base/openfpga_repack.cpp | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp index fef8dca89..6b7397a1c 100644 --- a/openfpga/src/base/openfpga_bitstream_command.cpp +++ b/openfpga/src/base/openfpga_bitstream_command.cpp @@ -21,6 +21,9 @@ ShellCommandId add_openfpga_repack_command(openfpga::Shell& she const ShellCommandClassId& cmd_class_id, const std::vector& dependent_cmds) { Command shell_cmd("repack"); + /* Add an option '--design_constraints' */ + CommandOptionId opt_design_constraints = shell_cmd.add_option("design_constraints", false, "file path to the design constraints"); + shell_cmd.set_option_require_value(opt_design_constraints, openfpga::OPT_STRING); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Enable verbose output"); diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp index a0fd143f4..b5a6d8a9a 100644 --- a/openfpga/src/base/openfpga_repack.cpp +++ b/openfpga/src/base/openfpga_repack.cpp @@ -8,10 +8,15 @@ /* Headers from openfpgashell library */ #include "command_exit_codes.h" +/* Headers from librepackdc library */ +#include "repack_design_constraints.h" +#include "read_xml_repack_design_constraints.h" + #include "build_physical_truth_table.h" #include "repack.h" #include "openfpga_repack.h" + /* Include global variables of VPR */ #include "globals.h" @@ -24,8 +29,17 @@ namespace openfpga { int repack(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { + CommandOptionId opt_design_constraints = cmd.option("design_constraints"); CommandOptionId opt_verbose = cmd.option("verbose"); + /* Load design constraints from file */ + RepackDesignConstraints repack_design_constraints; + if (true == cmd_context.option_enable(cmd, opt_design_constraints)) { + std::string dc_fname = cmd_context.option_value(cmd, opt_design_constraints); + VTR_ASSERT(false == dc_fname.empty()); + repack_design_constraints = read_xml_repack_design_constraints(dc_fname.c_str()); + } + pack_physical_pbs(g_vpr_ctx.device(), g_vpr_ctx.atom(), g_vpr_ctx.clustering(), From b86adabe694fdabd250e3c6110576a9bb2da5e5e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 21:14:52 -0700 Subject: [PATCH 15/24] [Lib] Remove unused data storage from repack design constraints --- .../repack_design_constraint_example.xml | 8 ++++---- .../read_xml_repack_design_constraints.cpp | 5 ----- .../src/repack_design_constraints.cpp | 19 ------------------- .../src/repack_design_constraints.h | 13 ------------- .../write_xml_repack_design_constraints.cpp | 2 -- 5 files changed, 4 insertions(+), 43 deletions(-) diff --git a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml index dbd2a04d1..4c0a8cdde 100644 --- a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml +++ b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml @@ -1,7 +1,7 @@ - - - - + + + + diff --git a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp index be63de6bc..315dac045 100644 --- a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp @@ -41,11 +41,6 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, repack_design_constraints.set_tile(design_constraint_id, get_attribute(xml_pin_constraint, "tile", loc_data).as_string()); - repack_design_constraints.set_tile_coordinate(design_constraint_id, - vtr::Point(get_attribute(xml_pin_constraint, "x", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1), - get_attribute(xml_pin_constraint, "y", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1))); - - openfpga::PortParser port_parser(get_attribute(xml_pin_constraint, "pin", loc_data).as_string()); repack_design_constraints.set_pin(design_constraint_id, diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.cpp b/libopenfpga/librepackdc/src/repack_design_constraints.cpp index ae395bef7..87e6aa48a 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/repack_design_constraints.cpp @@ -38,13 +38,6 @@ std::string RepackDesignConstraints::tile(const RepackDesignConstraintId& repack return repack_design_constraint_tiles_[repack_design_constraint_id]; } -vtr::Point RepackDesignConstraints::tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id) const { - /* validate the design_constraint_id */ - VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - return vtr::Point(repack_design_constraint_tiles_x_[repack_design_constraint_id], - repack_design_constraint_tiles_y_[repack_design_constraint_id]); -} - openfpga::BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); @@ -68,8 +61,6 @@ void RepackDesignConstraints::reserve_design_constraints(const size_t& num_desig repack_design_constraint_ids_.reserve(num_design_constraints); repack_design_constraint_types_.reserve(num_design_constraints); repack_design_constraint_tiles_.reserve(num_design_constraints); - repack_design_constraint_tiles_x_.reserve(num_design_constraints); - repack_design_constraint_tiles_y_.reserve(num_design_constraints); repack_design_constraint_pins_.reserve(num_design_constraints); repack_design_constraint_nets_.reserve(num_design_constraints); } @@ -81,8 +72,6 @@ RepackDesignConstraintId RepackDesignConstraints::create_design_constraint(const repack_design_constraint_ids_.push_back(repack_design_constraint_id); repack_design_constraint_types_.push_back(repack_design_constraint_type); repack_design_constraint_tiles_.emplace_back(); - repack_design_constraint_tiles_x_.push_back(size_t(-1)); - repack_design_constraint_tiles_y_.push_back(size_t(-1)); repack_design_constraint_pins_.emplace_back(); repack_design_constraint_nets_.emplace_back(); @@ -96,14 +85,6 @@ void RepackDesignConstraints::set_tile(const RepackDesignConstraintId& repack_de repack_design_constraint_tiles_[repack_design_constraint_id] = tile; } -void RepackDesignConstraints::set_tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id, - const vtr::Point& tile_coordinate) { - /* validate the design_constraint_id */ - VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - repack_design_constraint_tiles_x_[repack_design_constraint_id] = tile_coordinate.x(); - repack_design_constraint_tiles_y_[repack_design_constraint_id] = tile_coordinate.y(); -} - void RepackDesignConstraints::set_pin(const RepackDesignConstraintId& repack_design_constraint_id, const openfpga::BasicPort& pin) { /* validate the design_constraint_id */ diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.h b/libopenfpga/librepackdc/src/repack_design_constraints.h index e29fc228b..c8b917edb 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.h +++ b/libopenfpga/librepackdc/src/repack_design_constraints.h @@ -52,9 +52,6 @@ class RepackDesignConstraints { /* Get the tile name to be constrained */ std::string tile(const RepackDesignConstraintId& repack_design_constraint_id) const; - /* Get the tile coordinate to be constrained */ - vtr::Point tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id) const; - /* Get the pin to be constrained */ openfpga::BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const; @@ -76,10 +73,6 @@ class RepackDesignConstraints { void set_tile(const RepackDesignConstraintId& repack_design_constraint_id, const std::string& tile); - /* Set the tile coordinate to be constrained */ - void set_tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id, - const vtr::Point& tile_coordinate); - /* Set the pin to be constrained */ void set_pin(const RepackDesignConstraintId& repack_design_constraint_id, const openfpga::BasicPort& pin); @@ -100,12 +93,6 @@ class RepackDesignConstraints { /* Tiles to constraint */ vtr::vector repack_design_constraint_tiles_; - /* Coordinates of tiles to constraint - * Avoid using an object but a flatten way to be memory efficient - */ - vtr::vector repack_design_constraint_tiles_x_; - vtr::vector repack_design_constraint_tiles_y_; - /* Pins to constraint */ vtr::vector repack_design_constraint_pins_; diff --git a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp index f044d24d8..ba0a00eb3 100644 --- a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp @@ -43,8 +43,6 @@ int write_xml_pin_constraint(std::fstream& fp, } write_xml_attribute(fp, "tile", repack_design_constraints.tile(design_constraint).c_str()); - write_xml_attribute(fp, "x", repack_design_constraints.tile_coordinate(design_constraint).x()); - write_xml_attribute(fp, "y", repack_design_constraints.tile_coordinate(design_constraint).y()); write_xml_attribute(fp, "pin", generate_xml_port_name(repack_design_constraints.pin(design_constraint)).c_str()); write_xml_attribute(fp, "net", repack_design_constraints.net(design_constraint).c_str()); From bb8e7e25c2b5c41aa49f3ca6e83456a61cbd7814 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 21:27:12 -0700 Subject: [PATCH 16/24] [Tool] Start deploying design constraints in repack engine --- openfpga/src/base/openfpga_repack.cpp | 1 + openfpga/src/repack/repack.cpp | 10 +++++++++- openfpga/src/repack/repack.h | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp index b5a6d8a9a..872de054c 100644 --- a/openfpga/src/base/openfpga_repack.cpp +++ b/openfpga/src/base/openfpga_repack.cpp @@ -45,6 +45,7 @@ int repack(OpenfpgaContext& openfpga_ctx, g_vpr_ctx.clustering(), openfpga_ctx.mutable_vpr_device_annotation(), openfpga_ctx.mutable_vpr_clustering_annotation(), + repack_design_constraints, cmd_context.option_enable(cmd, opt_verbose)); build_physical_lut_truth_tables(openfpga_ctx.mutable_vpr_clustering_annotation(), diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 83956dfc9..958dd7545 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -339,6 +339,7 @@ void add_lb_router_nets(LbRouter& lb_router, const VprDeviceAnnotation& device_annotation, const ClusteringContext& clustering_ctx, const VprClusteringAnnotation& clustering_annotation, + const RepackDesignConstraints& design_constraints, const ClusterBlockId& block_id, const bool& verbose) { size_t net_counter = 0; @@ -542,6 +543,7 @@ void repack_cluster(const AtomContext& atom_ctx, const ClusteringContext& clustering_ctx, const VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const RepackDesignConstraints& design_constraints, const ClusterBlockId& block_id, const bool& verbose) { /* Get the pb graph that current clustered block is mapped to */ @@ -563,6 +565,7 @@ void repack_cluster(const AtomContext& atom_ctx, /* Add nets to be routed with source and terminals */ add_lb_router_nets(lb_router, lb_type, lb_rr_graph, atom_ctx, device_annotation, clustering_ctx, const_cast(clustering_annotation), + design_constraints, block_id, verbose); /* Initialize the modes to expand routing trees with the physical modes in device annotation @@ -607,12 +610,15 @@ void repack_clusters(const AtomContext& atom_ctx, const ClusteringContext& clustering_ctx, const VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const RepackDesignConstraints& design_constraints, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Repack clustered blocks to physical implementation of logical tile"); for (auto blk_id : clustering_ctx.clb_nlist.blocks()) { repack_cluster(atom_ctx, clustering_ctx, - device_annotation, clustering_annotation, + device_annotation, + clustering_annotation, + design_constraints, blk_id, verbose); } } @@ -632,6 +638,7 @@ void pack_physical_pbs(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const RepackDesignConstraints& design_constraints, const bool& verbose) { /* build the routing resource graph for each logical tile */ @@ -642,6 +649,7 @@ void pack_physical_pbs(const DeviceContext& device_ctx, /* Call the LbRouter to re-pack each clustered block to physical implementation */ repack_clusters(atom_ctx, clustering_ctx, const_cast(device_annotation), clustering_annotation, + design_constraints, verbose); } diff --git a/openfpga/src/repack/repack.h b/openfpga/src/repack/repack.h index 8121a58bd..3ca3a613f 100644 --- a/openfpga/src/repack/repack.h +++ b/openfpga/src/repack/repack.h @@ -8,6 +8,7 @@ #include "vpr_device_annotation.h" #include "vpr_clustering_annotation.h" #include "vpr_routing_annotation.h" +#include "repack_design_constraints.h" /******************************************************************** * Function declaration @@ -21,6 +22,7 @@ void pack_physical_pbs(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, VprDeviceAnnotation& device_annotation, VprClusteringAnnotation& clustering_annotation, + const RepackDesignConstraints& design_constraints, const bool& verbose); } /* end namespace openfpga */ From d0e05b3575736e58eee88d9ffad22c9d340a9b1e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 21:35:43 -0700 Subject: [PATCH 17/24] [Lib] Now use pb_type in design constraints instead of physical tiles --- .../repack_design_constraint_example.xml | 8 ++++---- .../src/read_xml_repack_design_constraints.cpp | 4 ++-- .../librepackdc/src/repack_design_constraints.cpp | 14 +++++++------- .../librepackdc/src/repack_design_constraints.h | 12 ++++++------ .../src/write_xml_repack_design_constraints.cpp | 2 +- .../config/repack_pin_constraints.xml | 8 ++++---- 6 files changed, 24 insertions(+), 24 deletions(-) diff --git a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml index 4c0a8cdde..a2f270da8 100644 --- a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml +++ b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml @@ -1,7 +1,7 @@ - - - - + + + + diff --git a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp index 315dac045..47f10a156 100644 --- a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp @@ -38,8 +38,8 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, "Fail to create design constraint!\n"); } - repack_design_constraints.set_tile(design_constraint_id, - get_attribute(xml_pin_constraint, "tile", loc_data).as_string()); + repack_design_constraints.set_pb_type(design_constraint_id, + get_attribute(xml_pin_constraint, "pb_type", loc_data).as_string()); openfpga::PortParser port_parser(get_attribute(xml_pin_constraint, "pin", loc_data).as_string()); diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.cpp b/libopenfpga/librepackdc/src/repack_design_constraints.cpp index 87e6aa48a..d19c1ba71 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/repack_design_constraints.cpp @@ -32,10 +32,10 @@ RepackDesignConstraints::e_design_constraint_type RepackDesignConstraints::type( return repack_design_constraint_types_[repack_design_constraint_id]; } -std::string RepackDesignConstraints::tile(const RepackDesignConstraintId& repack_design_constraint_id) const { +std::string RepackDesignConstraints::pb_type(const RepackDesignConstraintId& repack_design_constraint_id) const { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - return repack_design_constraint_tiles_[repack_design_constraint_id]; + return repack_design_constraint_pb_types_[repack_design_constraint_id]; } openfpga::BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const { @@ -60,7 +60,7 @@ bool RepackDesignConstraints::empty() const { void RepackDesignConstraints::reserve_design_constraints(const size_t& num_design_constraints) { repack_design_constraint_ids_.reserve(num_design_constraints); repack_design_constraint_types_.reserve(num_design_constraints); - repack_design_constraint_tiles_.reserve(num_design_constraints); + repack_design_constraint_pb_types_.reserve(num_design_constraints); repack_design_constraint_pins_.reserve(num_design_constraints); repack_design_constraint_nets_.reserve(num_design_constraints); } @@ -71,18 +71,18 @@ RepackDesignConstraintId RepackDesignConstraints::create_design_constraint(const repack_design_constraint_ids_.push_back(repack_design_constraint_id); repack_design_constraint_types_.push_back(repack_design_constraint_type); - repack_design_constraint_tiles_.emplace_back(); + repack_design_constraint_pb_types_.emplace_back(); repack_design_constraint_pins_.emplace_back(); repack_design_constraint_nets_.emplace_back(); return repack_design_constraint_id; } -void RepackDesignConstraints::set_tile(const RepackDesignConstraintId& repack_design_constraint_id, - const std::string& tile) { +void RepackDesignConstraints::set_pb_type(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& pb_type) { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - repack_design_constraint_tiles_[repack_design_constraint_id] = tile; + repack_design_constraint_pb_types_[repack_design_constraint_id] = pb_type; } void RepackDesignConstraints::set_pin(const RepackDesignConstraintId& repack_design_constraint_id, diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.h b/libopenfpga/librepackdc/src/repack_design_constraints.h index c8b917edb..e770c5542 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.h +++ b/libopenfpga/librepackdc/src/repack_design_constraints.h @@ -49,8 +49,8 @@ class RepackDesignConstraints { /* Get the type of constraint */ e_design_constraint_type type(const RepackDesignConstraintId& repack_design_constraint_id) const; - /* Get the tile name to be constrained */ - std::string tile(const RepackDesignConstraintId& repack_design_constraint_id) const; + /* Get the pb_type name to be constrained */ + std::string pb_type(const RepackDesignConstraintId& repack_design_constraint_id) const; /* Get the pin to be constrained */ openfpga::BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const; @@ -69,9 +69,9 @@ class RepackDesignConstraints { /* Add a design constraint to storage */ RepackDesignConstraintId create_design_constraint(const e_design_constraint_type& repack_design_constraint_type); - /* Set the tile name to be constrained */ - void set_tile(const RepackDesignConstraintId& repack_design_constraint_id, - const std::string& tile); + /* Set the pb_type name to be constrained */ + void set_pb_type(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& pb_type); /* Set the pin to be constrained */ void set_pin(const RepackDesignConstraintId& repack_design_constraint_id, @@ -91,7 +91,7 @@ class RepackDesignConstraints { vtr::vector repack_design_constraint_types_; /* Tiles to constraint */ - vtr::vector repack_design_constraint_tiles_; + vtr::vector repack_design_constraint_pb_types_; /* Pins to constraint */ vtr::vector repack_design_constraint_pins_; diff --git a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp index ba0a00eb3..ec8f662fb 100644 --- a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp @@ -42,7 +42,7 @@ int write_xml_pin_constraint(std::fstream& fp, return 1; } - write_xml_attribute(fp, "tile", repack_design_constraints.tile(design_constraint).c_str()); + write_xml_attribute(fp, "pb_type", repack_design_constraints.pb_type(design_constraint).c_str()); write_xml_attribute(fp, "pin", generate_xml_port_name(repack_design_constraints.pin(design_constraint)).c_str()); write_xml_attribute(fp, "net", repack_design_constraints.net(design_constraint).c_str()); diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml index ed4a49775..b64eafee5 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml @@ -6,9 +6,9 @@ - the clk[2] port of all the clb tiles available in the FPGA fabric - the clk[3] port of all the clb tiles available in the FPGA fabric --> - - - - + + + + From 2efe513122808f3f44b828f495f215fc10fee04c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 21:57:17 -0700 Subject: [PATCH 18/24] [Tool] Now repack consider design constraints; test pending --- .../src/repack_design_constraints.h | 3 +++ openfpga/src/repack/repack.cpp | 27 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.h b/libopenfpga/librepackdc/src/repack_design_constraints.h index e770c5542..c32a0aca8 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.h +++ b/libopenfpga/librepackdc/src/repack_design_constraints.h @@ -17,6 +17,9 @@ #include "repack_design_constraints_fwd.h" +/* Constants */ +constexpr char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN"; + /******************************************************************** * A data structure to describe the design constraints for repacking tools * This data structure may include a number of design constraints diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 958dd7545..b6c458430 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -410,6 +410,33 @@ void add_lb_router_nets(LbRouter& lb_router, /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; + + /* Check if the net information is constrained or not */ + std::string constrained_net_name; + for (const RepackDesignConstraintId& design_constraint : design_constraints.design_constraints()) { + /* All the pin must have only 1 bit */ + VTR_ASSERT_SAFE(1 == design_constraints.pin(design_constraint).get_width()); + /* If found a constraint, record the net name */ + if ( (std::string(lb_type->pb_type->name) == design_constraints.pb_type(design_constraint)) + && (std::string(source_pb_pin->port->name) == design_constraints.pin(design_constraint).get_name()) + && (size_t(source_pb_pin->pin_number) == design_constraints.pin(design_constraint).get_lsb())) { + constrained_net_name = design_constraints.net(design_constraint); + break; + } + } + /* If the pin is constrained, we need to + * - if this is an open net, for invalid net then + * - if this is valid net name, find the net id from atom_netlist and overwrite the atom net id to mapped + */ + if (!constrained_net_name.empty()) { + if (std::string(REPACK_DESIGN_CONSTRAINT_OPEN_NET) == constrained_net_name) { + atom_net_id == AtomNetId::INVALID(); + } else { + VTR_ASSERT_SAFE(std::string(REPACK_DESIGN_CONSTRAINT_OPEN_NET) != constrained_net_name); + atom_net_id = atom_ctx.nlist.find_net(constrained_net_name); + } + } + /* Bypass unmapped pins */ if (AtomNetId::INVALID() == atom_net_id) { continue; From 12e0efd03ef5b8878ae9d9987086203679ca17ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 17 Jan 2021 10:33:56 -0700 Subject: [PATCH 19/24] [Script] Add an example openfpga script to use repack design constraints --- ...al_tile_multiclock_example_script.openfpga | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga new file mode 100644 index 000000000..847f55939 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINTS_FILE} #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From dd74f05a314fe8798b0da356325082ab14b4512d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 17 Jan 2021 10:35:36 -0700 Subject: [PATCH 20/24] [Test] Add repack constraints to tests --- .../global_tile_ports/global_tile_4clock/config/task.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index 943976ece..c99c73823 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -22,9 +22,10 @@ fpga_flow=vpr_blif #fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml +openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml From 113119bd8e746768bef924d51435300f827112d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 17 Jan 2021 10:39:55 -0700 Subject: [PATCH 21/24] [Lib] Fix the bug in repack design constraint parser --- .../librepackdc/src/read_xml_repack_design_constraints.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp index 47f10a156..dbf773748 100644 --- a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp @@ -66,7 +66,7 @@ RepackDesignConstraints read_xml_repack_design_constraints(const char* design_co try { loc_data = pugiutil::load_xml(doc, design_constraint_fname); - pugi::xml_node xml_root = get_single_child(doc, "repack_design_constraint", loc_data); + pugi::xml_node xml_root = get_single_child(doc, "repack_design_constraints", loc_data); size_t num_design_constraints = std::distance(xml_root.children().begin(), xml_root.children().end()); /* Reserve memory space for the region */ From ea9d6bfe91a0cefd27f0bbdda57441c222b5670a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 17 Jan 2021 10:41:01 -0700 Subject: [PATCH 22/24] [Flow] Update the design constraint file to follow bug fix in parser --- .../dc_example/repack_design_constraint_example.xml | 4 ++-- .../global_tile_4clock/config/repack_pin_constraints.xml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml index a2f270da8..c63a5b815 100644 --- a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml +++ b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml @@ -1,7 +1,7 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml index b64eafee5..d695cf85e 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml @@ -1,4 +1,4 @@ - +