riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

minor change in variable names in lb_router

This commit is contained in:
tangxifan 2020-03-11 21:10:16 -06:00
parent 8e796f152f
commit 17a1c61b9d
2 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
openfpga/src/repack/lb_router.cpp
View File

@ -237,24 +237,24 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
unsigned int inet; unsigned int inet;
/* Iterate across all nets internal to logic block */ /* Iterate across all nets internal to logic block */
for (inet = 0; inet < lb_net_ids_.size() && !is_impossible; inet++) { for (inet = 0; inet < lb_net_ids_.size() && !is_impossible; inet++) {
NetId idx = NetId(inet); NetId net_idx = NetId(inet);
if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[idx])) { if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
continue; continue;
} }
commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[idx], RT_REMOVE, mode_map); commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_REMOVE, mode_map);
free_net_rt(lb_net_rt_trees_[idx]); free_net_rt(lb_net_rt_trees_[net_idx]);
lb_net_rt_trees_[idx] = nullptr; lb_net_rt_trees_[net_idx] = nullptr;
add_source_to_rt(idx); add_source_to_rt(net_idx);
/* Route each sink of net */ /* Route each sink of net */
for (unsigned int itarget = 1; itarget < lb_net_terminals_[idx].size() && !is_impossible; itarget++) { for (unsigned int itarget = 1; itarget < lb_net_terminals_[net_idx].size() && !is_impossible; itarget++) {
pq_.clear(); pq_.clear();
/* Get lowest cost next node, repeat until a path is found or if it is impossible to route */ /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
expand_rt(idx, idx); expand_rt(net_idx, net_idx);
is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, idx, exp_node, itarget, mode_status_.expand_all_modes, verbosity); is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, itarget, mode_status_.expand_all_modes, verbosity);
if (is_impossible && !mode_status_.expand_all_modes) { if (is_impossible && !mode_status_.expand_all_modes) {
mode_status_.try_expand_all_modes = true; mode_status_.try_expand_all_modes = true;
@ -262,15 +262,15 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
break; break;
} }
if (exp_node.node_index == lb_net_terminals_[idx][itarget]) { if (exp_node.node_index == lb_net_terminals_[net_idx][itarget]) {
/* Net terminal is routed, add this to the route tree, clear data structures, and keep going */ /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
is_impossible = add_to_rt(lb_net_rt_trees_[idx], exp_node.node_index, idx); is_impossible = add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
} }
if (is_impossible) { if (is_impossible) {
VTR_LOG("Routing was impossible!\n"); VTR_LOG("Routing was impossible!\n");
} else if (mode_status_.expand_all_modes) { } else if (mode_status_.expand_all_modes) {
is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[idx]); is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx]);
if (is_impossible) { if (is_impossible) {
VTR_LOG("Routing was impossible due to modes!\n"); VTR_LOG("Routing was impossible due to modes!\n");
} }
@ -288,7 +288,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
} }
if (!is_impossible) { if (!is_impossible) {
commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[idx], RT_COMMIT, mode_map); commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_COMMIT, mode_map);
if (mode_status_.is_mode_conflict) { if (mode_status_.is_mode_conflict) {
is_impossible = true; is_impossible = true;
} }

2
openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
View File

@ -218,7 +218,7 @@
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 --> <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
<port name="in" physical_mode_port="in[0:4]"/> <port name="in" physical_mode_port="in[0:4]"/>
<port name="out" physical_mode_port="lut5_out" physical_mode_pin_rotate_offset="1"/> <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type> </pb_type>
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0"> <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">