From 16e02ef48574ea4e6f59c3882b7b79540b8c80f2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 16 Apr 2021 20:47:39 -0600
Subject: [PATCH] [Arch] patch architectures to be consistent with port mapping
 of custom DFF in yosys script

---
 .../k4_frac_N4_fracff_40nm_cc_openfpga.xml    |  8 +--
 .../k4_frac_N4_tileable_fracff_40nm.xml       | 50 +++++++++----------
 2 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
index 7d3ea06b4..5aca72a87 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
@@ -145,9 +145,9 @@
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="RST" size="1" default_val="0"/>
+       <port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0"/>
+       <port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
     </circuit_model>
     <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -197,10 +197,10 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0">
+    <global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
       <tile name="clb" port="clk"/>
     </global_port>
-    <global_port name="reset" is_reset="true" default_val="0">
+    <global_port name="op_reset" is_reset="true" default_val="0">
       <tile name="clb" port="reset"/>
     </global_port>
   </tile_annotations>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
index f9d57e4ca..af701b3c9 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
@@ -46,12 +46,12 @@
     <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
     <model name="dffr">
       <input_ports>
-        <port name="D" clock="clk"/>
-        <port name="RST" clock="clk"/>
-        <port name="clk" is_clock="1"/>
+        <port name="D" clock="C"/>
+        <port name="R" clock="C"/>
+        <port name="C" is_clock="1"/>
       </input_ports>
       <output_ports>
-        <port name="Q" clock="clk"/>
+        <port name="Q" clock="C"/>
       </output_ports>
     </model>
   </models>
@@ -284,18 +284,18 @@
             <!-- Define flip-flop -->
             <pb_type name="ff" blif_model=".subckt dffr" num_pb="2">
               <input name="D" num_pins="1" port_class="D"/>
-              <input name="RST" num_pins="1"/>
+              <input name="R" num_pins="1"/>
               <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_setup value="66e-12" port="ff.RST" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <clock name="C" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="C"/>
+              <T_setup value="66e-12" port="ff.R" clock="C"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
               <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
-              <complete name="direct4" input="fabric.reset" output="ff[1:0].RST"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].C"/>
+              <complete name="direct4" input="fabric.reset" output="ff[1:0].R"/>
               <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
@@ -350,12 +350,12 @@
               <!-- Define the flip-flop -->
               <pb_type name="ff" blif_model=".subckt dffr" num_pb="1">
                 <input name="D" num_pins="1" port_class="D"/>
-                <input name="RST" num_pins="1"/>
+                <input name="R" num_pins="1"/>
                 <output name="Q" num_pins="1" port_class="Q"/>
-                <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                <T_setup value="66e-12" port="ff.RST" clock="clk"/>
-                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                <clock name="C" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="C"/>
+                <T_setup value="66e-12" port="ff.R" clock="C"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
               </pb_type>
               <interconnect>
                 <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@@ -363,8 +363,8 @@
                   <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
                   <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
                 </direct>
-                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
-                <direct name="direct4" input="ble3.reset" output="ff[0:0].RST"/>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].C"/>
+                <direct name="direct4" input="ble3.reset" output="ff[0:0].R"/>
                 <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
                   <!-- LUT to output is faster than FF to output on a Stratix IV -->
                   <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
@@ -420,12 +420,12 @@
             <!-- Define flip-flop -->
             <pb_type name="ff" blif_model=".subckt dffr" num_pb="1">
               <input name="D" num_pins="1" port_class="D"/>
-              <input name="RST" num_pins="1" port_class="D"/>
+              <input name="R" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_setup value="66e-12" port="ff.RST" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <clock name="C" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="C"/>
+              <T_setup value="66e-12" port="ff.R" clock="C"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
@@ -433,8 +433,8 @@
                 <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
                 <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
               </direct>
-              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
-              <direct name="direct4" input="ble4.reset" output="ff.RST"/>
+              <direct name="direct3" input="ble4.clk" output="ff.C"/>
+              <direct name="direct4" input="ble4.reset" output="ff.R"/>
               <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>