From 16de60e9439399b1b7b7e638f131162143472f18 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 12:31:14 -0700 Subject: [PATCH] [Test] Turn off ACE2 run in bitstream generation only flows --- .../generate_bitstream_fix_device_example_script.openfpga | 2 +- .../generate_bitstream/device_48x48/config/task.conf | 4 ++-- .../generate_bitstream/device_96x96/config/task.conf | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga index 9558a5944..e5c963ecf 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf index 22f2f94a4..a66a1a273 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true # Runtime of this bitstream generation should not exceed 3 minutes as a QoR requirement @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_route_chan_width=50 openfpga_vpr_device_layout=48x48 diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf index 45903d9e6..e5708fba4 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true # Runtime of this bitstream generation should not exceed 6 minutes as a QoR requirement @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_route_chan_width=100 openfpga_vpr_device_layout=96x96