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Fix minor changes in page

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bbleaptrot 2021-03-23 18:19:14 -06:00 committed by GitHub
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docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst
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@ -64,7 +64,7 @@ This error log can be found by running the following command from the root direc
cat openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/00_and2_MIN_ROUTE_CHAN_WIDTH_out.log
This command failed during the verification step because the path to the module definition for ADDF is missing. In our architecture file, user-defined verilog modules are those ``<circuit_model>`` with the key term verilog_netlist. The `user_defined_templates.v` file provides a module template for incorporating Hard IPs with no external library into the architecture.
This command failed during the verification step because the path to the module definition for ADDF is missing. In our architecture file, user-defined verilog modules are those ``<circuit_model>`` with the key term `verilog_netlist`. The ``user_defined_templates.v`` file provides a module template for incorporating Hard IPs with no external library into the architecture.
Fixing the Error
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